AT25DL081-MHN-T Adesto Technologies, AT25DL081-MHN-T Datasheet - Page 41

• Manufacturer Part Number: AT25DL081-MHN-T
• Description: Flash 8M 1.65-1.95V 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DL081-MHN-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 8 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Current: 20 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UDFN-8

12.
12.1
Other Commands and Functions
Reset
In some applications, it may be necessary to prematurely terminate a program or erase cycle rather than wait the
hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The
Reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle
state. Since the need to reset the device is immediate, the Write Enable command does not need to be issued prior to the
Reset command. Therefore, the Reset command operates independently of the state of the WEL bit in the Status
Register.
The Reset command can be executed only if the command has been enabled by setting the Reset Enabled (RSTE) bit in
the Status Register to a Logical 1. If the Reset command has not been enabled (the RSTE bit is in the Logical 0 state),
then any attempts at executing the Reset command will be ignored.
To perform a Reset, the CS pin must first be asserted, and then the opcode F0h must be clocked into the device. No
address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device immediately after the
opcode. Any additional data clocked into the device after the confirmation byte will be ignored. When the CS pin is
deasserted, the program or erase operation currently in progress will be terminated within a time of t
program or erase operation may not complete before the device is reset, the contents of the page being programmed or
the block being erased cannot be guaranteed to be valid.
The Reset command has no effect on the states of the Sector Protection Registers, the Sector Lockdown Registers, the
Configuration Register, or the SPRL, RSTE, and SLE bits in the Status Register. The WEL, PS, and ES bits of the Status
Register, however, will be reset back to their default states. If a Reset operation is performed while a sector is erase
suspended, the suspend operation will abort, and the contents of the block being erased in the suspended sector will be
left in an undefined state. If a Reset is performed while a sector is program suspended, the suspend operation will abort,
and the contents of the page that was being programmed and subsequently suspended will be undefined. The remaining
pages in the 64KB sector will retain their previous contents.
The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS
pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be
performed.
Figure 12-1. Reset
SCK
SO
CS
SI
MSB
High-impedance
1
0
1
1
1
2
Opcode
1
3
0
4
0
5
0
6
0
7
MSB
1
8
Confirmation Byte In
1
9
0
10 11
1
0
12
0
13
0
14 15
0
AT25DL081 [DATASHEET]
8732E–DFLASH–1/2013
RST
. Since the
41