AT45DB321D-CCU Adesto Technologies, AT45DB321D-CCU Datasheet
AT45DB321D-CCU
Specifications of AT45DB321D-CCU
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AT45DB321D-CCU Summary of contents
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... Unique 64-byte device identifier ● JEDEC standard manufacturer and device ID read ● 100,000 program/erase cycles per page, minimum ● Data retention: 20 years ● Industrial temperature range ● Green (Pb/halide-free/RoHS compliant) packaging options AT45DB321D 32Mb, 2.5V or 2.7V DataFlash DATASHEET 3597R–DFLASH–11/2012 ...
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... Description The AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the RapidS serial interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz. ...
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... CC voltages may produce spurious results and should not be Asserted State Type Low Input – Input – Input – Output Low Input Low Input – Output – Power – Ground AT45DB321D [DATASHEET] 3 3597R–DFLASH–11/2012 ...
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... RDY/BUSY 2. Memory Array To provide optimal flexibility, the AT45DB321D memory array is divided into three levels of granularity comprising sectors, blocks, and pages. The “Memory Architecture Diagram” pages per sector and block. All program operations to the DataFlash device occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block, or page level ...
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... A valid instruction starts with the falling edge of CS, diagrams in this datasheet for details on the clock cycle sequences for specification. The continuous array read bypasses CAR1 . To perform a continuous read array with the page size set to 528 bytes, CAR1 Section 22., Detailed Bit-level Read AT45DB321D [DATASHEET] 5 3597R–DFLASH–11/2012 ...
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... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO perform a continuous read array with the page size set to 528 bytes, the CS must CAR2 specification. The main memory page read SCK AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 . CAR2 6 ...
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... The erase operation is internally self-timed, and should take place in a maximum time of t status register and the RDY/BUSY pin will indicate that the part is busy. . During this EP . During this time, the status P . During this time, the PE AT45DB321D [DATASHEET] 7 3597R–DFLASH–11/2012 ...
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... ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 1020 1021 1022 1023 . During this time, SE AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 8 ...
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... ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● During CE Byte 3 Byte 4 80H 9AH AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 9 ...
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... Figure 6-1. Enable Sector Protection CS Opcode SI Byte 1 Each transition represents 8 bits . During this time, the status register and the RDY/BUSY pin will EP Byte 1 3DH Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 Byte 2 Byte 3 Byte 4 2AH 7FH A9H AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 10 ...
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... Opcode Opcode Byte 2 Byte 3 Byte 4 time. However, when the WP pin is deasserted, sector protection would no WPE time) as long as the enable sector protection command was not issued WPD 2 Byte 2 Byte 3 Byte 4 2AH 7FH 9AH , then the CC 3 AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 11 ...
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... Enabled Read/write Disabled Read/write Enabled Read/write Table 7-3 illustrates the format of the sector FFH 00H 0b Bit 5, 4 Bit 3, 2 Bit ® is 00H. AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 Data Value 0xH CxH 3xH FxH 12 ...
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... Byte 1 3DH Byte 2 Byte 3 2AH 7FH 7.1, the sector protection register contains 64 bytes of , during which the status register P Byte 2 Byte 3 2AH 7FH AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 Byte 4 CFH Byte 4 FCH 13 ...
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... Opcode Opcode Opcode Data byte byte 2 byte 3 byte 4 n Byte 1 32H Data byte n Data byte Data byte Byte 2 Byte 3 Byte 4 xxH xxH xxH Data byte Data byte AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 14 ...
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... Bit Byte 3 Byte 4 7FH 30H Address Address bytes bytes FFH 00H 0b Bit 5, 4 Bit 3, 2 Bit AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 Data Value 00H C0H 30H F0H 15 ...
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... X X Data byte n Security Register Byte Number 1 · · · One-time user programmable Byte 2 Byte 3 Byte 4 xxH xxH xxH Data byte Data byte · · · 126 Adesto factory programmed AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 127 16 ...
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... Opcode Opcode Opcode Data byte byte 2 byte 3 byte Data byte n , during which the status register will indicate P Data byte Data byte Data byte Data byte AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 17 ...
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... Adesto for availability of devices that are specified to exceed the 20,000 cycle cumulative limit. XFR Figure 23-2, page 42 is recommended. Each page within a sector must be ), the status register can be read or the ), the status register and the COMP Figure AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 23-1, 18 ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB321D, the four bits are 1101. The decimal value of these four binary bits does not equate to the device density — the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... Figure 10-2. Resume from Deep Power-Down CS SI Opcode Each transition represents 8 bits . Once the device has entered the deep power-down mode, all EDPD Opcode B9H time before the device can receive any commands. RDPD Opcode ABH AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 20 ...
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... The fourth byte output will be the extended device information string length, which will be 00H to indicate that no extended Byte 1 3DH Opcode Opcode Opcode byte 2 byte 3 byte 4 Section 24., “Ordering Information” during which time the status P Byte 2 Byte 3 Byte 4 2AH 80H A6H AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 21 ...
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... Manufacturer ID 1FH = Adesto Family code 001 = DataFlash Density code 00111 = 32Mb MLC code 000 = 1-bit/cell technology Product version 00001 = Second version Byte count 00H = 0 bytes of Information Data Extended device information Byte AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 22 ...
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... However, during the internally self-timed portion of group B commands, any command in group C can be executed. The group B commands using buffer 1 should use group C commands using buffer 2, and vice versa. Finally, during the internally self-timed portion of a group D command, only the status register read command should be executed. AT45DB321D [DATASHEET] 23 3597R–DFLASH–11/2012 ...
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... C7H, 94H, 80H, 9AH 82H 85H Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H 3DH + 2AH + 7FH + 30H 35H 9BH + 00H + 00H + 00H 77H AT45DB321D [DATASHEET] 24 3597R–DFLASH–11/2012 ...
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... Main memory page read Continuous array read Status register read Note: 1. These legacy commands are not recommended for new designs. Opcode 53H 55H 60H 61H 58H 59H B9H ABH D7H 9FH Opcode 54H 56H 52H 68H 57H AT45DB321D [DATASHEET] 25 3597R–DFLASH–11/2012 ...
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... N/A N/A N N/A AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 Bytes N/A 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4 N/A ...
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... N/A N/A N N/A AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 Bytes N/A 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...
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... CC VCSL rises above the power-on reset threshold value (V CC Min 70 1.5 . During VCSL rises above the power-on reset CC ) before the device can POR Typ Max Unit μ 2.5 V AT45DB321D [DATASHEET] 28 3597R–DFLASH–11/2012 ...
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... Voltage Extremes referenced in the "Absolute Maximum Ratings" are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any + 0.6V CC extended period of time. AT45DB321D (2.5V Version) -40°C to 85°C 2.5V to 3.6V Condition CS, RESET all inputs at CMOS levels ...
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... TBD TBD TBD AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 Max Unit 66 MHz 66 MHz 33 MHz ns ns V/ns V/ 100 μs 1 μs 3 μs 35 μs 300 μ ...
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... Waveform 1 shows the SCK signal being low when CS makes a high-to CSH Valid out Timing waveforms 1 and 2 conform to WL period. These timing waveforms are valid DIS High impedance AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 31 ...
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... Valid CSH 66MHz) MAX CSH Valid out 66MHz) MAX CSH t HO Valid out DIS High impedance DIS High impedance DIS High impedance AT45DB321D [DATASHEET] 32 3597R–DFLASH–11/2012 ...
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... SI (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted LSB BYTE-MOSI F High impedance MSB BYTE-SO t REC t CSS t RST High impedance AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 1 LSB 33 ...
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... Page address Byte/Buffer address (PA12 - PA0) (BA9 - BA0/BFA9 - BFA0) Flash Memory Array Buffer 2 (512-/528-bytes) I/O Interface SI LSB LSB Buffer 2 to Main Memory Page Program Buffer 2 WRITE AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 34 ...
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... CMD PA12-6 PA5-0, XX Flash Memory Array Buffer 2 (512-/528-bytes) Main Memory Page Read I/O Interface SO Completes writing into selected buffer n n+1 Last byte XXXX 1st byte read n+1 = 2nd byte read Main Memory Page to Buffer 2 Buffer 2 Read AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 35 ...
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... Starts reading page data into buffer Binary Page Size A21- Don't care bits PA12-6 PA5-0, XX Binary Page Size 15 Don't care + Bfa8-bfa0 X BFA7 X..X, BFA9-8 No dummy byte (opcodes D1H and D3H) 1 dummy byte (opcodes D4H and D6H) AT45DB321D [DATASHEET n+1 XXXX XXXX n n+1 36 3597R–DFLASH–11/2012 ...
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... Don't care Data byte MSB Data byte MSB AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 MSB Bit 0 of Page N MSB 37 ...
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... X X Data byte MSB MSB Data byte MSB MSB MSB AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 38 ...
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... Don't care MSB Data byte MSB MSB MSB MSB AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 39 ...
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... Status register data Status register data MSB MSB Device Id byte 1 Device Id byte 2 00H MSB 38 AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 40 ...
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... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. START Provide Address and Data Buffer Write (84h, 87h) Buffer to Main Memory Page Program (83h, 86h) END AT45DB321D [DATASHEET] 41 3597R–DFLASH–11/2012 ...
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... If planning to modify multiple to Buffer Transfer bytes currently stored within (53h, 55h) a page of the Flash array Buffer Write (84h, 87h) Buffer to Main Memory Page Program (83h, 86h) (2) Auto Page Rewrite (58h, 59h) Increment Page (2) Address Pointer END AT45DB321D [DATASHEET] 42 3597R–DFLASH–11/2012 ...
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... Package Option M = 8-pad 1mm MLF (VDFN 8-pad 1mm MLF (VDFN 8-lead, 0.209" wide SOIC T = 28-lead, TSOP Ball BGA Voltage f (MHz) Operation Range SCK 66 Industrial (-40C to 85C) 2. ™ (VDFN) AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 43 ...
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... Lead Package (VDFN) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – 0.85 1.00 A1 – – 0.05 A2 0.65 TYP A3 0.20 TYP b 0.35 0.40 0.48 D 5.90 6.00 6.10 D1 5.70 5.75 5.80 D2 3.20 3.40 3.60 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 3.80 4.00 4.20 e 1.27 L 0.50 0.60 0.75 0 – – 0.25 – – GPC DRAWING NO. YBR 8M1-A AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 8/28/08 REV ...
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... Body, Very Thin Dual Flat Package No Lead (MLF) SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOM – – 1.00 A1 – – 0.05 b 0.35 0.40 0.48 D 7.90 8.00 8.10 D1 6.30 6.40 6.50 E 5.90 6.00 6.10 E1 4.70 4.80 4.90 e 1.27 L 0.45 0.50 0.55 K 0.30 REF 5/25/ WING 8MW B AT45DB321D [DATASHEET] 3597R–DFLASH–11/2012 45 ...
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... Body, Plastic Small Package Drawing Contact: Outline Package (EIAJ) contact@adestotech.com END VIEW END VIEW SYMBOL AT45DB321D [DATASHEET COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOM NOTE 1.70 2.16 0.05 0.25 0.35 0.48 4 0.15 0.35 4 5.13 5.35 5.18 5. ...
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... TITLE 28T, 28-lead (8 x 13.4mm) Plastic Thin Small Outline Package, Type I (TSOP GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE – – 1.20 0.05 – 0.15 0.90 1.00 1.05 13.20 13.40 13.60 11.70 11.80 11.90 Note 2 7.90 8.00 8.10 Note 2 0.50 0.60 0.70 0.25 BASIC 0.17 0.22 0.27 0.10 – 0.21 0.55 BASIC 12/06/02 DRAWING NO. REV. 28T C AT45DB321D [DATASHEET] 47 3597R–DFLASH–11/2012 ...
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... TITLE 24C3, 24-ball ( Array), 1.0 mm Pitch 1.20 mm, Chip-scale Ball Grid Array Package (CBGA) COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE 5.90 6.00 6.10 4.0 TYP 7.90 8.00 8.10 4.0 TYP – – 1.20 0.25 – – 1.00 BSC 0.40 TYP 9/10/04 DRAWING NO. REV. 24C3 A AT45DB321D [DATASHEET] 48 3597R–DFLASH–11/2012 ...
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... Removed “not recommended for new designs” note from ordering information for 8MW package 3597F 08/2006 Added errata regarding Chip Erase Added AT45DB321D-SU to ordering information and corresponding 8S2 package 3597E 07/2006 Corrected typographical errors 3597D 04/2006 Added 8 x 6mm MLF (VDFN) package ...
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... Use block erase (opcode 50H alternative. The block erase function is not affected by the chip erase issue. 27.1.3 Resolution The chip erase feature may be fixed with a new revision of the device. Please contact Adesto for the estimated availability of devices with the fix. AT45DB321D [DATASHEET] 50 3597R–DFLASH–11/2012 ...
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... Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...