M24LR04E-RDW6T/2 STMicroelectronics, M24LR04E-RDW6T/2 Datasheet - Page 31

• Manufacturer Part Number: M24LR04E-RDW6T/2
• Description: EEPROM 4-Kbit Dual EEPROM 1.8 to 5.5V 13.56Mhz
• Manufacturer: STMicroelectronics

Specifications of M24LR04E-RDW6T/2

• Product Category: EEPROM
• Memory Size: 4 Kbit
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Current: 20 uA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Factory Pack Quantity: 1

M24LR04E-R
5
5.1
5.2
5.3
5.4
5.5
I
The device supports the I
data to the bus is defined as a transmitter, and any device that reads data is defined as a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which also
provides the serial clock for synchronization. The M24LR04E-R device is a slave in all
communications.
Start condition
Start is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable
in the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a write cycle) the SDA and the SCL for a Start
condition, and does not respond unless one is given.
Stop condition
Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal write cycle.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases the serial data (SDA) after sending eight
bits of data. During the 9
the receipt of the eight data bits.
Data input
During data input, the device samples serial data (SDA) on the rising edge of the serial clock
(SCL). For correct device operation, the SDA must be stable during the rising edge of the
SCL, and the SDA signal must change only when the SCL is driven low.
I²C timeout
During the execution of an I²C operation, RF communications are not possible.
To prevent RF communication freezing due to inadvertent unterminated instructions sent to
the I²C bus, the M24LR04E-R features a timeout mechanism that automatically resets the
I²C logic block.
2
C device operation
th
2
C protocol. This is summarized in
clock pulse period, the receiver pulls the SDA low to acknowledge
Doc ID 022208 Rev 5
Figure
4. Any device that sends
I
2
C device operation
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