M24LR04E-RMC6T/2 STMicroelectronics, M24LR04E-RMC6T/2 Datasheet

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... RF: 5.75 ms including the internal Verify time More than 1 million write cycles More than 40-year data retention Multiple password protection in RF mode Single password protection in I Package – ECOPACK2 Halogen-free) Doc ID 022208 Rev 5 M24LR04E-R Datasheet production data SO8 (MN) 150 mils width TSSOP8 (DW mode 2 C mode ® ...

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... Antenna coil (AC0, AC1 2.5.1 2.6 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SS 2.7 Supply voltage (V 2.7.1 2.7.2 2.7.3 2.7.4 3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 M24LR04E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.1 4.2 M24LR04E-R block security in I²C mode (I2C_Write_Lock bit area 4.3 Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 ...

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... Communication signal from VCD to M24LR04E Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 Data coding mode: 1 out 9.3 VCD to M24LR04E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . present password command description . . . . . . . . . . . . . . . . . . . . . 39 ...

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... Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.1 11.1.2 11.2 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2.1 11.2.2 12 M24LR04E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1.1 12.1.2 12.2 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.2.1 12.2.2 12.3 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.1 12.3.2 12.4 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 ...

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... Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.1 t1: M24LR04E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25 VCD new request delay when no response is received 3 from the M24LR04E Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Doc ID 022208 Rev 4 Contents 5/142 ...

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... Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 26.23 ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.24 WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 26.25 WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 26.26 SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 26.27 CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 27 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 29 RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 31 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6/142 Doc ID 022208 Rev 4 M24LR04E-R ...

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... M24LR04E-R Appendix A Anticollision algorithm (informative 137 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Appendix B CRC (informative 138 B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Appendix C Application family identifier (AFI) (informative 140 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Doc ID 022208 Rev 4 Contents 7/142 ...

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... Response data rates Table 21. UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 22. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 23. VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 24. M24LR04E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 25. M24LR04E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 26. General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 27. Definition of request flags Table 28. Request flags when Bit Table 29 ...

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... M24LR04E-R Table 49. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 50. Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 88 Table 51. Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 52. Select Block response format when Error_flag is NOT set Table 53. Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 54. Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 55. ...

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... Table 128. TSSOP8 – 8-lead thin shrink small outline, package mechanical data 135 Table 129. Ordering information scheme for bare die devices or packaged devices . . . . . . . . . . . . . 136 Table 130. CRC definition 138 Table 131. AFI coding 140 Table 132. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10/142 Doc ID 022208 Rev 4 M24LR04E-R ...

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... End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 58 Figure 45. End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 47. M24LR04E-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 = 400 kHz): maximum R value versus bus parasitic bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 022208 Rev 4 ...

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... List of figures Figure 48. M24LR04E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 49. M24LR04E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 50. Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 73 Figure 51. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 52. M24LR04E RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . 81 Figure 53. Stay Quiet frame exchange between VCD and M24LR04E Figure 54 ...

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... It features an I also a contactless memory powered by the received carrier electromagnetic wave. The M24LR04E-R is organized as 512 × 8 bits in the I The M24LR04E-R also features an energy harvesting analog output, as well as a user- configurable digital output pin toggling during either RF write in progress or RF busy mode. Figure 1. ...

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... Data are transferred from the M24LR04E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR04E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz ...

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... This configurable output signal is used either to indicate that the M24LR04E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR04E-R is powered by the Vcc pin open drain output and a pull up resistor must be connected from RF WIP/BUSY ...

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... Supply voltage (V This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allows the external voltage applied on V M24LR04E-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V 2.7.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V ...

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... M24LR04E-R 2 Figure Fast mode (f capacitance (C 100 10 Here R bus × C bus = 120 Figure bus protocol SCL SDA SCL SDA Start Condition SCL SDA = 400 kHz): maximum bus 30 pF 100 1000 Bus line capacitor (pF) SDA SDA Start ...

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... Signal descriptions Table 2. Device select code Device select code 1. The most significant bit, b7, is sent first not connected to any external pin however used to address the M24LR04E-R as described in Section 3 and Section Table 3. Address most significant byte b15 b14 Table 4. Address least significant byte ...

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... M24LR04E-R 3 User memory organization The M24LR04E-R is divided into 4 sectors of 32 blocks of 32 bits, as shown in Figure 6 shows the memory sector organization. Each sector can be individually read- and/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector. ...

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... Sector details The M24LR04E-R user memory is divided into 4 sectors. Each sector contains 1024 bits. The protection scheme is described mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to the 32 blocks contained in the sector ...

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... M24LR04E-R Table 5. Sector details Sector RF block number address byte Bits [31:24] address 0 0 user 1 4 user 2 8 user 3 12 user 4 16 user 5 20 user 6 24 user 7 28 user 8 32 ...

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... Doc ID 022208 Rev 5 M24LR04E-R Bits [23:16] Bits [15:8] Bits [7:0] user user user user user user user user user user user user user user user user ... ... ... ... ...

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... M24LR04E-R block security in RF mode The M24LR04E-R provides a special protection mechanism based on passwords mode, each memory sector of the M24LR04E-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set. Each memory sector of the M24LR04E-R is assigned with a Sector security status byte ...

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... Password control bits The M24LR04E-R password protection is organized around a dedicated set of commands, plus a system area of three password blocks where the password values are stored. This system area is described in Table 10. Password system area Add The dedicated commands for protection in RF mode are: ...

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... M24LR04E-R Present-sector password: The Present-sector password command is used to present one of the three passwords to the M24LR04E-R in order to modify the access rights of all the memory sectors linked to that password password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated ...

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... When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF busy mode. The purpose of this mode is to indicate to the I²C bus master whether the M24LR04E-R is busy in RF mode or not. In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF) until the end of the command execution ...

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... The M24LR04E-R features an Energy harvesting mode on the Vout analog output. The general purpose of the Energy harvesting mode is to deliver a part of the non- necessary RF power received by the M24LR04E-R on the AC0-AC1 RF input in order to supply an external device. The current consumption on the analog voltage output Vout is limited to ensure that the M24LR04E-R is correctly supplied during the powering of the external device ...

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... FIELD_ON indicator bit The FIELD_ON bit indicator located as Bit 1 of the Control register is a read-only bit used to indicate when the RF power level delivered to the M24LR04E-R is sufficient to execute RF commands. When FIELD_ON = 0, the M24LR04E-R is not able to execute any RF commands. When FIELD_ON =1, the M24LR04E-R is able to execute any RF commands. ...

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... Set/reset energy harvesting enable bit command (SetRstEHEn): The SetRstEHEn command is used to set or reset the value of the EH_enable bit into the Control register. 4.4 ISO 15693 system parameters The M24LR04E-R provides the system area required by the ISO 15693 RF protocol, as shown in Table 17. The first 32-bit block starting from I ...

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... UID (02h) RFU Mem_Size 2332 (FFh) Doc ID 022208 Rev location 2322, and the DSFID Bits [15: password (1) RF password 1 (1) RF password 2 (1) RF password 3 ST reserved UID UID UID (03 7F) M24LR04E Bits [7:0] Configuration byte (F4h) UID UID IC Ref (5A) ...

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... The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The M24LR04E-R device is a slave in all communications. ...

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... Table 2 (on Serial Data (SDA), most significant bit first). Only one memory device can be connected on a single I²C bus. In M24LR04E-R, E1 and E0 are internally set to 1. The eighth bit is the Read/Write bit (RW set to 1 for Read and to 0 for Write operations. ...

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... M24LR04E-R Table 18. Operating modes Mode Byte write Page write Figure 8. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited) Byte Write Page Write Page Write (cont'd) RW bit Bytes 0 1 Start, device select bytes Start, device select ACK ACK ...

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... After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. 34/142 , and the successful completion of a Write operation, W Figure 9. Doc ID 022208 Rev 5 M24LR04E-R Figure 8, and waits for two (Table 4). Bits b15 to b0 form ...

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... M24LR04E-R Figure 9. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) ACK Byte Write Dev Select R/W ACK Page Write Dev Select R/W Figure 10. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device ReStart Stop ACK ACK ...

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... Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 36/142 , but the typical time is shorter. To make use of this, a polling sequence Figure 10, is: Doc ID 022208 Rev 5 M24LR04E ...

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... M24LR04E-R Figure 11. Read mode sequences Current Address Read Random Address Read Sequential Current Read Sequential Random Read 1. The seven most significant bits of the device select code of a random read (in the first and fourth bytes) must be identical. ACK NO ACK Dev select Data out ...

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... For all Read commands, the device waits, after each byte read, for an acknowledgment during the ninth bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 38/142 Figure 11. Doc ID 022208 Rev 5 M24LR04E-R ...

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... It is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR04E-R does not start the internal comparison. When the bus master generates a Stop condition immediately after the Ack bit (during the tenth bit time slot), an internal delay equivalent to the write cycle time is triggered ...

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... I C write password command description 2 The I C write password command is used to write a 32-bit block into the M24LR04E-R I password system area. This command is used in I value. It cannot be used to update any of the RF passwords. After the write cycle, the new password value is automatically activated. The I ...

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... Energy Harvesting Configuration byte: F4h Bit 7 to bit 4: all set to 1 Bit 3: set to 0 (RF BUSY mode on RF WIP/BUSY pin) Bit 2: set to 1 (Energy harvesting not activated by default) Bit 1 and bit 0: set to 0 (fan-out setting) M24LR04E-R memory initial state Doc ID 022208 Rev 5 41/142 ...

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... RF device operation 7 RF device operation The M24LR04E-R is divided into 4 sectors of 32 blocks of 32 bits, as shown in sector can be individually read- and/or write-protected using a specific lock or password command. Read and Write operations are possible if the addressed block is not protected. During a Write, the 32 bits of the block are replaced by the new 32-bit value. ...

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... Commands The M24LR04E-R supports the following commands: Inventory, used to perform the anticollision sequence. Stay quiet, used to put the M24LR04E-R in quiet mode, where it does not respond to any inventory command. Select, used to select the M24LR04E-R. After this command, the M24LR04E-R processes all Read/Write commands with Select_flag set. ...

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... Power transfer Power is transferred to the M24LR04E-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR04E-R and the VCD. The RF operating field of the VCD is transformed on the M24LR04E-R antenna voltage which is rectified, filtered and internally regulated. During communications, the amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator ...

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... Depending on the choice made by the VCD, a “pause” is created as described in and Figure 15. The M24LR04E-R is operational for the 100% modulation index or for any degree of modulation index between 10% and 30% (see Figure 14. 100% modulation waveform Carrier Amplitude ...

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... Communication signal from VCD to M24LR04E-R Table 19. 10% modulation parameters Symbol hr hf Figure 15. 10% modulation waveform Carrier Carrier Amplitude Amplitude Modulation Modulation Modulation Index Index Index The VICC shall be operational for any value of modulation index between 10 % and 30 %. ...

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... Data rate and data coding The data coding implemented in the M24LR04E-R uses pulse position modulation. Both data coding modes that are described in the ISO15693 are supported by the M24LR04E-R. The selection is made by the VCD and indicated to the M24LR04E-R within the start of frame (SOF). 9.1 Data coding mode: 1 out of 256 The value of one single byte is represented by the position of one pause ...

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... Figure 19 48/142 . . . . . Figure 18 illustrates the 1 out of 4 pulse position technique and shows the transmission of E1h (225d - 1110 0001b) by the VCD. Doc ID 022208 Rev 5 M24LR04E-R 9.44 µs 18.88 µ Time Period one of 256 AI06657 ) determines the value of the two bits. ...

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... M24LR04E-R Figure 18. 1 out of 4 coding mode Pulse position for "00" 9.44 µs 9.44 µs Pulse position for "01" (1=LSB) Pulse position for "10" (0=LSB) Pulse position for "11" Figure 19. 1 out of 4 coding example 10 75.52µs 75.52 µs 28.32 µs 9.44 µs 75.52 µ ...

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... Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are implemented using code violation. Unused options are reserved for future use. The M24LR04E-R is ready to receive a new command frame from the VCD 311.5 µs (t after sending a response frame to the VCD. ...

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... M24LR04E-R Figure 22. EOF for either data coding mode 9.44µs 9.44µs 37.76µs Doc ID 022208 Rev 5 Data rate and data coding AI06662 51/142 ...

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... Data rates The M24LR04E-R can respond using the low or the high data rate format. The selection of the data rate is made by the VCD using the second bit in the protocol header. For fast commands, the selected data rate is multiplied by two. ...

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... M24LR04E-R 11 Bit representation and coding Data bits are encoded using Manchester coding, according to the following schemes. For the low data rate, same subcarrier frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4 and all times increase by this factor. For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2 ...

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... For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by 16 pulses at 423.75 kHz (f Figure 30. Logic 1, low data rate, fast commands 54/142 /32) followed by an unmodulated time of C Figure 27. 151.04µs Figure 75.52µs Figure 29. 151.04µs /32), as shown in Figure C 75.52µs Doc ID 022208 Rev 5 M24LR04E-R ai12068 /32) followed 28. ai12069 ai12070 30. ai12071 ...

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... M24LR04E-R 11.2 Bit coding using two subcarriers 11.2.1 High data rate A logic 0 starts with eight pulses at 423.75 kHz (f 484.28 kHz (f /28), as shown in C for the Fast commands. Figure 31. Logic 0, high data rate A logic 1 starts with nine pulses at 484.28 kHz (f 423.75 kHz (f /32), as shown in C for the Fast commands ...

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... M24LR04E-R to VCD frames 12 M24LR04E-R to VCD frames Frames are delimited by an SOF and an EOF. They are implemented using code violation. Unused options are reserved for future use. For the low data rate, the same subcarrier frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4. ...

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... C Figure 226.56µs /28), followed by 24 pulses at 423.75 kHz C Figure 39. 112.39µs 37.46µs /28), followed by 96 pulses at 423.75 kHz C Figure 40. 449.56µs Doc ID 022208 Rev 5 M24LR04E-R to VCD frames 38. 75.52µs ai12081 ai12082 149.84µs ai12083 57/142 ...

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... M24LR04E-R to VCD frames 12.3 EOF when using one subcarrier 12.3.1 High data rate The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and an unmodulated time of 18.88 µs, followed by 24 pulses at 423.75 kHz (f of 56.64 µs, as shown in Figure 41. End of frame, high data rate, one subcarrier 37.76µ ...

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... Bit coding using two subcarriers is not supported for the Fast commands. Figure 46. End of frame, low data rate, two subcarriers 149.84µs Figure 45. 37.46µs 112.39µs Figure 46. Doc ID 022208 Rev 5 M24LR04E-R to VCD frames /32) and 27 pulses at 484.28 kHz C ai12088 /32) and 108 pulses at 484.28 kHz C 449.56µs ai12089 59/142 ...

Page 60

... Unique identifier (UID) 13 Unique identifier (UID) The M24LR04E-R is uniquely identified by a 64-bit unique identifier (UID). This UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and comprises: eight MSBs with a value of E0h, the IC manufacturer code “ST 02h” bits (ISO/IEC 7816-6/AM1), a unique serial number on 48 bits ...

Page 61

... Figure 47. M24LR04E-R decision tree for AFI The AFI is programmed by the M24LR04E-R issuer (or purchaser) in the AFI register. Once programmed and locked, it can no longer be modified. The most significant nibble of the AFI is used to code one specific or all application families. ...

Page 62

... EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field. Upon reception of a request from the VCD, the M24LR04E-R verifies that the CRC value is valid invalid, the M24LR04E-R discards the frame and does not answer to the VCD. Upon reception of a response from the M24LR04E- recommended that the VCD verifies whether the CRC value is valid ...

Page 63

... VCD and the M24LR04E-R in both directions based on the concept of “VCD talks first”. This means that an M24LR04E-R does not start transmitting unless it has received and properly decoded an instruction sent by the VCD. The protocol is based on an exchange of: a request from the VCD to the M24LR04E-R, a response from the M24LR04E-R to the VCD ...

Page 64

... M24LR04E-R protocol description Figure 48. M24LR04E-R protocol timing Request VCD (Table M24LR04 E-R Timing 64/142 frame 23) Response frame (Table 24) <-t -> <-t 1 Doc ID 022208 Rev 5 M24LR04E-R Request frame (Table 23) Response frame (Table -> <-t -> 24) <-t -> 2 ...

Page 65

... Quiet Selected Transitions between these states are specified in 17.1 Power-off state The M24LR04E the Power-off state when it does not receive enough energy from the VCD. 17.2 Ready state The M24LR04E the Ready state when it receives enough energy from the VCD. When in the Ready state, the M24LR04E-R answers any request where the Select_flag is not set ...

Page 66

... Address_Flag is set AND where Inventory_Flag is not set 1. The M24LR04E-R returns to the Power Off state if the tag is out of the RF field for at least t refer to application note AN4125 for more information. 2. The intention of the state transition method is that only one M24LR04E-R should be in the Selected state at a time ...

Page 67

... Select_flag set to 1 executes it and returns a response to the VCD as specified in the command description. Only M24LR04E-Rs in the Selected state answer a request where the Select_flag set to 1. The system design ensures in theory that only one M24LR04E-R can be in the Select state at a time. Doc ID 022208 Rev 5 ...

Page 68

... F 19.1 Request flags In a request, the “flags” field specifies the actions to be performed by the M24LR04E-R and whether corresponding fields are present or not. The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the contents of the four MSBs (bits 5 to 8). When bit 3 is reset (0), bits define the M24LR04E-R selection criteria ...

Page 69

... Request is executed only by the M24LR04E-R in Selected state Request is not addressed. UID field is not present. The request is 0 executed by all M24LR04E-Rs. (1) Request is addressed. UID field is present. The request is 1 executed only by the M24LR04E-R whose UID matches the UID specified in the request. 0 Option not activated. 1 Option activated. 0 ...

Page 70

... General response format S O Response_flags F 20.1 Response flags In a response, the flags indicate how actions have been performed by the M24LR04E-R and whether corresponding fields are present or not. The response flags consist of eight bits. Table 31. Definitions of response flags Bit No Bit 1 Error_flag Bit 2 ...

Page 71

... M24LR04E-R 20.2 Response error code If the Error_flag is set by the M24LR04E-R in the response, the Error code field is present and provides information about the error that occurred. Error codes not specified in Table 32. Response error code definition Error code 03h 0Fh 10h 11h 12h 13h ...

Page 72

... Anticollision 21 Anticollision The purpose of the anticollision sequence is to inventory the M24LR04E-Rs present in the VCD field using their unique ID (UID). The VCD is the master of communications with one or several M24LR04E-Rs. It initiates M24LR04E-R communication by issuing the Inventory request. The M24LR04E-R sends its response in the determined slot or does not respond. ...

Page 73

... The first slot starts immediately after the request EOF is received. To switch to the next slot, the VCD sends an EOF. The following rules and restrictions apply M24LR04E-R answer is detected, the VCD may switch to the next slot by sending an EOF. If one or more M24LR04E-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot ...

Page 74

... Request processing by the M24LR04E-R 22 Request processing by the M24LR04E-R Upon reception of a valid request, the M24LR04E-R performs the following algorithm: NbS is the total number of slots ( the current slot number (0 to 15) LSB (value, n) function returns the n Less Significant Bits of value MSB (value, n) function returns the n Most Significant Bits of value “ ...

Page 75

... The VCD sends an Inventory request frame terminated by an EOF. The number of slots is 16. M24LR04E-R_1 transmits its response in Slot the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD. The VCD sends an EOF in order to switch to the next slot. ...

Page 76

Slot 0 Inventory VCD SOF EOF EOF Request Response M24RF64s Response Response 1 Timing Comment Collision collision Time Slot 1 Slot 2 Slot 3 Request to EOF EOF SOF M24RF64_1 Response 2 4 Response 3 5 ...

Page 77

... M24LR04E-R 24 Inventory Initiated command The M24LR04E-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer to Inventory Initiated commands. For applications in which multiple tags are moving in front of a reader possible to miss tags using the standard inventory command ...

Page 78

... EOF from the M24LR04E-Rs. The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR04E- also the time after which the VCD may send a new request to the M24LR04E- described in Figure ...

Page 79

... M24LR04E-R 26 Command codes The M24LR04E-R supports the commands described in this section. Their codes are given in Table 36. Table 36. Command codes Command code standard 01h 02h 20h 21h 23h 25h 26h 27h 28h 29h 2Ah 2Bh Function Inventory Stay Quiet Read Single Block ...

Page 80

... Inventory response format Response Response_ SOF flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value min = 4384/f ...

Page 81

... F RF_Busy 2) Slot n never occurs. RF_Busy is only released by Power-off command F RF_Busy 3) VCD sends a Valid command before slot n. RF_Busy is released after M24LR04E response RF_Busy 4) VCD sends a Bad command (unknown command code, false CRC...) before slot n. RF_Busy is released after VCD command. S ...

Page 82

... Command codes 26.2 Stay Quiet Command code = 0x02 On receiving the Stay Quiet command, the M24LR04E-R enters the Quiet State if no error occurs, and does NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs. When in the Quiet state: the M24LR04E-R does not process any request if the Inventory_flag is set, the M24LR04E-R processes any Addressed request ...

Page 83

... M24LR04E-R 26.3 Read Single Block On receiving the Read Single Block command, the M24LR04E-R reads the requested block and sends back its 32-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. Table 40. Read Single Block request format Request ...

Page 84

... The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. During the RF write cycle W otherwise, the M24LR04E-R may not program correctly the data into the memory. The W time is equal to t 1nom Table 44. ...

Page 85

... R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write Single Block command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid write single block command to the beginning of the M24LR04E-R response) ...

Page 86

... Command codes Figure 56. M24LR04E RF-Busy management following Write command 1) M24LR04E replies. RF_Busy is released after M24LR04E response command F RF_Busy 2) M24LR04E replies when option flag is set. RF_Busy is released after M24LR04E response command F RF_Busy 3) VCD sends a forbidden Write (sector lock, password-protected). RF_Busy is released after M24LR04E command ...

Page 87

... Write & verify sequence, as shown in Figure 57. M24LR04E RF-Wip management following Write command 1) M24LR04E replies. RF_Wip is released after M24LR04E response command F RF_Wip 2) M24LR04E replies when option flag is set. RF_Wip is released after M24LR04E response command F RF_Wip 3) VCD sends a forbidden Write (sector lock, password-protected). RF_Wip remains at a high impedance ...

Page 88

... The maximum number of blocks is fixed at 32 assuming that they are all located in the same sector. If the number of blocks overlaps sectors, the M24LR04E-R returns an error code. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. ...

Page 89

... If the UID does not match its own, the selected M24LR04E-R returns to the Ready state and does not send a response. The M24LR04E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated error occurs, the M24LR04E-R remains in its current state. ...

Page 90

... Figure 59. Select frame exchange between VCD and M24LR04E-R VCD M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Select command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 90/142 ...

Page 91

... M24LR04E-R 26.7 Reset to Ready On receiving a Reset to Ready command, the M24LR04E-R returns to the Ready state if no error occurs. In the Addressed mode, the M24LR04E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. Table 54. Reset to Ready request format Request Request_ ...

Page 92

... On receiving the Write AFI request, the M24LR04E-R programs the 8-bit AFI value to its memory. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR04E-R may not write correctly the AFI value into the memory. The W time is equal to t 1nom Table 57. ...

Page 93

... Write AFI command to the beginning of the M24LR04E-R response). 26.9 Lock AFI On receiving the Lock AFI request, the M24LR04E-R locks the AFI value permanently. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR04E-R may not Lock correctly the AFI value in memory. The W equal × ...

Page 94

... M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock AFI command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of valid Lock AFI command to the beginning of the M24LR04E-R response) ...

Page 95

... Write DSFID On receiving the Write DSFID request, the M24LR04E-R programs the 8-bit DSFID value to its memory. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR04E-R may not write correctly the DSFID value in memory. The W time is equal to t 1nom Table 63. ...

Page 96

... Lock DSFID On receiving the Lock DSFID request, the M24LR04E-R locks the DSFID value permanently. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR04E-R may not lock correctly the DSFID value in memory. The W is equal × 302 µs. 1nom Table 66. ...

Page 97

... M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock DSFID command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Lock DSFID command to the beginning of the M24LR04E-R response) ...

Page 98

... Command codes 26.12 Get System Info When receiving the Get System Info command, the M24LR04E-R sends back its information data in the response.The Option_flag is not supported. The Get System Info can be issued in both Addressed and Non Addressed modes. The Protocol_extension_flag must be set to 0. ...

Page 99

... VCD M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get System Info command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. Get System Info ...

Page 100

... The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. During the M24LR04E-R response, if the internal block address counter reaches 01FFh, it rolls over to 0000h and the Sector Security Status bytes for that location are sent back to the reader ...

Page 101

... VCD M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get Multiple Block Security Status command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. ...

Page 102

... Figure 67. Write-sector Password frame exchange between VCD and M24LR04E-R VCD M24LR04E-R M24LR04E-R 102/142 Response_flags 8 bits ...

Page 103

... Care must be taken when issuing the Lock- sector command as all the blocks belonging to the same sector are automatically locked by a single command. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. During the RF write cycle W otherwise, the M24LR04E-R may not correctly lock the memory block. The × ...

Page 104

... The Option_flag is supported. During the comparison cycle equal to W 10%), otherwise, the M24LR04E-R the Password value may not be correctly compared. The W time is equal ...

Page 105

... M24LR04E-R Table 83. Present-sector Password request format Request Request SOF _flags 8 bits 1. Gray means that the field is optional. Request parameter: Request flags UID (optional) Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error) Password Table 84. Present-sector Password response format when Error_flag is NOT set ...

Page 106

... SOF M24LR04E-R M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Present Sector Password command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY remains in high-Z state. 106/142 Present- ...

Page 107

... The Option_flag is supported. The data rate of the response is multiplied by 2. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code. Table 86. ...

Page 108

... Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR04E-R does not answer to the Fast Inventory Initiated command. The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code. On receiving the Fast Inventory Initiated request, the M24LR04E-R runs the anticollision sequence ...

Page 109

... Fast Inventory Initiated response format Response Response SOF _flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value ...

Page 110

... Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR04E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR04E-R. The data rate of the response is multiplied by 2. The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code ...

Page 111

... If the number of blocks overlaps sectors, the M24LR04E-R returns an error code. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. The Option_flag is supported. The data rate of the response is multiplied by 2. The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code. Table 94. ...

Page 112

... Inventory Initiated Before receiving the Inventory Initiated command, the M24LR04E-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR04E-R does not answer to the Inventory Initiated command. On receiving the Inventory Initiated request, the M24LR04E-R runs the anticollision sequence ...

Page 113

... Inventory Initiated response format Response Response SOF _flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value ...

Page 114

... The command has to be issued in the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR04E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR04E-R. ...

Page 115

... On receiving the ReadCfg command, the M24LR04E-R reads the Configuration byte and sends back its 8-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag the M24LR04E-R answers with an error code. The Option_flag is not supported. The Inventory_flag must be set to 0. ...

Page 116

... If the Protocol_extension_flag the M24LR04E-R answers with an error code. The Option_flag is supported, the Inventory_flag is not supported. During the RF write cycle W otherwise, the M24LR04E-R may not program correctly the data into the Configuration byte. The W time is equal Table 105. WriteEHCfg request format ...

Page 117

... On receiving the WriteDOCfg command, the M24LR04E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag the M24LR04E-R answers with an error code ...

Page 118

... M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the WriteEHCfg command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of a valid WriteDOCfg command to the beginning of the M24LR04E-R response) ...

Page 119

... M24LR04E-R 26.26 SetRstEHEn On receiving the SetRstEHEn command, the M24LR04E-R sets or resets the EH_enable bit in the volatile Control register. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag the M24LR04E-R answers with an error code. The Option_flag and the Inventory_flag are not supported. ...

Page 120

... On receiving the CheckEHEn command, the M24LR04E-R reads the Control register and sends back its 8-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag the M24LR04E-R answers with an error code. The Option_flag is not supported. The Inventory_flag must be set to 0. ...

Page 121

... Figure 78. CheckEHEn frame exchange between VCD and M24LR04E-R VCD M24LR04E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the CheckEHEn command to the end of the M24LR04E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. Error code ...

Page 122

... Parameter Sawn wafer on UV tape UFDFPN8 (MLP8), SO8, TSSOP8 UFDFPN8 (MLP8), SO8, TSSOP8 VAC0-VAC1 VAC0-GND, or VAC1-GND AC0, AC1 (4) Other pads Doc ID 022208 Rev 5 M24LR04E-R Min. Max. Unit –40 85 ° °C (1) 6 months kept in its original packing form – ...

Page 123

... M24LR04E and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device in I tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...

Page 124

... 2 SDA connected to V CC. Doc ID 022208 Rev 5 M24LR04E-R Min. Max ± 2 ± ± 100 kHz 400 kHz c 100 = 400 kHz c 200 = 400 kHz ...

Page 125

... M24LR04E-R 2 Table 122 characteristics Symbol Alt SCL t t CHCL HIGH t t CLCH LOW t START_OU T ( XH1XH2 R ( XL1XL2 DL1DL2 DXCX SU:DAT t t CLDX HD:DAT t t CLQX DH (4)( CLQV AA ( CHDX SU:STA t t DLCL HD:STA ...

Page 126

... SDA In tCHDH Stop condition SCL tCLQV SDA Out 126/142 tCHCL tCLCH tCLDX tDXCX SDA Change SDA Input tW Write cycle tCHCL tCLQX Data valid Data valid Doc ID 022208 Rev 5 M24LR04E-R tXL1XL2 tCHDH tDHDL Stop Start condition condition tCHDX Start condition tDL1DL2 AI00795e ...

Page 127

... RFSBL Minimum time from carrier t MIN CD generation to first data f Subcarrier frequency high SH f Subcarrier frequency low SL t Time for M24LR04E-R response 1 t Time between commands 2 RF write time (including internal W t Verify) I Operating current (Read) CC_RF C ...

Page 128

... Symbol T Ambient operating temperature A Figure 81 shows an ASK modulated signal from the VCD to the M24LR04E-R. The test condition for the AC/DC parameters are: Close coupling condition with tester antenna (1 mm) M24LR04E-R performance measured at the tag antenna M24LR04E-R synchronous timing, transmit and receive 128/142 ...

Page 129

... M24LR04E-R Figure 81. ASK modulated signal Table 125 below summarizes respectively the minimum AC0-AC1 input power level P required for the Energy harvesting mode, the corresponding maximum current AC1_min consumption I sink_max harvesting fan-out configurations defined by bits b0 and b1 of the Configuration byte. Table 125. Energy harvesting ...

Page 130

... RF electrical parameters Figure 82. Vout vs. Isink Figure 83. Range 11 domain Fan out ( 0.3 mA 130/142 1 A/m 1.6 A/m 2.4 A/m Doc ID 022208 Rev 5 M24LR04E-R MS19777V1 Working domain when Range 11 is selected Field 3.5 A/m 5 A/m (Hrms) MS19790V1 ...

Page 131

... M24LR04E-R Figure 84. Range 10 domain Fan out ( 0.3 mA Figure 85. Range 01 domain Fan out ( 0 A/m 1.6 A/m 2.4 A/m 1 A/m 1.6 A/m 2.4 A/m Doc ID 022208 Rev 5 RF electrical parameters Working domain when Range 10 is selected Field 3.5 A/m 5 A/m (Hrms) MS19791V1 Working domain when Range 01 is selected Field 3 ...

Page 132

... RF electrical parameters Figure 86. Range 00 domain Fan out ( 0.3 mA 132/142 1 A/m 1.6 A/m 2.4 A/m Doc ID 022208 Rev 5 M24LR04E-R Working domain when Range 00 is selected Field 3.5 A/m 5 A/m (Hrms) MS19793V1 ...

Page 133

... M24LR04E-R 30 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline 1. Drawing is not to scale. Table 126. SO8N – ...

Page 134

... Doc ID 022208 Rev 5 M24LR04E Pin must not be allowed to SS (1) inches Typ Min 0.0217 0.0177 0.0008 0.0000 ...

Page 135

... M24LR04E-R Figure 89. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 128. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits. ...

Page 136

... Option T = Tape and reel packing Capacitance / Delivery type: wafer tested, unsawn, without backgrinding. Wafer thickness: 725 µm ±20 µm. Bad chip identification by STIF wafer maps provided by STMicroelectronics. 2. For packaged devices only. 136/142 M24LR04E-R MN (1) Doc ID 022208 Rev 5 M24LR04E ...

Page 137

... M24LR04E-R is inventoried then store (M24LR04E-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ...

Page 138

... CRC (informative) B.1 CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR04E- R and from M24LR04E-R to VCD. Table 130. CRC definition CRC type ...

Page 139

... M24LR04E-R number_of_databytes = NUMBER_OF_BYTES; } else // check CRC { number_of_databytes = NUMBER_OF_BYTES + 2; } current_crc_value = PRESET_VALUE; for ( < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for ( < 8; j++) { if (current_crc_value & 0x0001) { POLYNOMIAL; } else { } } } if (calculate_or_check_crc == CALC_CRC) { current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\n", current_crc_value); // current_crc_value is now ready to be appended to the data ...

Page 140

... Application family identifier (AF (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR04E-Rs present only the M24LR04E-R meeting the required application criteria programmed by the M24LR04E-R issuer (the purchaser of the M24LR04E-R). Once locked, it cannot be modified ...

Page 141

... Table 125: Energy harvesting table. 2 Replaced figures 82 to 86. 3 Changed datasheet status to “Full datasheet”. Updated Table 122: I2C AC characteristics 4 numbering. 5 Updated Figure 49: M24LR04E-R state transition diagram on page Doc ID 022208 Rev 5 Revision history Changes and added note under the and Section 31: Part 141/142 66. ...

Page 142

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 142/142 Please Read Carefully: © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 022208 Rev 4 M24LR04E-R ...