LPC1313FHN33/01,51 NXP Semiconductors, LPC1313FHN33/01,51 Datasheet - Page 35

• Manufacturer Part Number: LPC1313FHN33/01,51
• Description: ARM Microcontrollers - MCU CortexM3 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC1313FHN33/01,51

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1313
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 4000

NXP Semiconductors
Table 7.
T
[1]
[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[12] Including voltage on outputs in 3-state mode.
[13] V
[18] Includes external resistors of 33 Ω ± 1 % on USB_DP and USB_DM.
Table 8.
T
[1]
[2]
LPC1311_13_42_43
Product data sheet
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To V
[17] 3.0 V ≤ V
Symbol
V
C
E
E
E
E
E
R
R
Symbol Parameter
V
C
Z
amb
amb
DRV
OH
IA
D
L(adj)
O
G
T
trans
ia
vsi
i
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
For LPC1342 and LPC1343 only: For USB operation 3.0 V ≤ V
IRC enabled; system oscillator disabled; system PLL disabled.
I
BOD disabled.
All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in
the syscon block.
For LPC1342/43: USB_DP and USB_DM pulled LOW externally.
IRC disabled; system oscillator enabled; system PLL enabled.
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
DD
= −40 °C to +85 °C, unless otherwise specified.
= −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, V
DD
measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
SS
supply voltage must be present.
.
HIGH-level output
voltage
transceiver capacitance pin to GND
driver output
impedance for driver
which is not high-speed
capable
Static characteristics
ADC static characteristics
DD
Parameter
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
gain error
absolute error
voltage source interface
resistance
input resistance
≤ 3.6 V.
D
) is the difference between the actual step width and the ideal step width. See
…continued
Conditions
driven; for low-/full-speed;
R
with 33 Ω series resistor; steady state
drive
L
of 15 kΩ to GND
All information provided in this document is subject to legal disclaimers.
Conditions
Rev. 5 — 6 June 2012
DD
≤ 3.6 V. Guaranteed by design.
[1][2]
[7][8]
[3]
[4]
[5]
[6]
[18][17]
Min
0
-
-
-
-
-
-
-
-
[17]
[17]
32-bit ARM Cortex-M3 microcontroller
DD
LPC1311/13/42/43
= 2.5 V to 3.6 V.
Min
2.8
-
36
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
[1]
Max
V
1
±1
±1.5
±3.5
0.6
±4
40
2.5
Figure
© NXP B.V. 2012. All rights reserved.
DD
Max
3.5
20
44.1
8.
Unit
V
pF
LSB
%
LSB
kΩ
MΩ
LSB
LSB
35 of 74
Unit
V
pF
Ω