LPC1313FHN33/01,51 NXP Semiconductors, LPC1313FHN33/01,51 Datasheet - Page 20

• Manufacturer Part Number: LPC1313FHN33/01,51
• Description: ARM Microcontrollers - MCU CortexM3 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC1313FHN33/01,51

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1313
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 4000

NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.9.1.1 Features
7.9.1 Full-speed USB device controller
7.9 USB interface (LPC1342/43 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1342/43 USB interface is a device controller with on-chip PHY for device
functions.
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Table 5.
Logical
endpoint
0
0
1
1
2
2
3
3
4
4
•
•
•
•
•
•
•
•
On the LPC1311/13/42/43, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up
to 2.6 V (V
On the LPC1311/01 and LPC1313/01, all GPIO pins (except PIO0_4 and PIO0_5) are
pulled up to 3.3 V (V
block.
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per
endpoint (see
Supports Control, Bulk, Isochronous, and Interrupt endpoints.
Supports SoftConnect feature.
Double buffer implementation for Bulk and Isochronous endpoints.
USB device endpoint configuration
Physical
endpoint
0
1
2
3
4
5
6
7
8
9
DD
All information provided in this document is subject to legal disclaimers.
= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.
Table
Endpoint type
Control
Control
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Isochronous
Isochronous
Rev. 5 — 6 June 2012
5).
DD
= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG
Direction
out
in
out
in
out
in
out
in
out
in
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
64
64
64
64
512
512
Packet size
(byte)
64
64
64
64
© NXP B.V. 2012. All rights reserved.
Double buffer
no
no
no
no
no
no
yes
yes
yes
yes
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