LPC1313FHN33/01,51 NXP Semiconductors, LPC1313FHN33/01,51 Datasheet - Page 27

• Manufacturer Part Number: LPC1313FHN33/01,51
• Description: ARM Microcontrollers - MCU CortexM3 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC1313FHN33/01,51

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1313
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 4000

NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.18.5.1 Power profiles (LPC1300L series, LPC1311/01 and LPC1313/01 only)
7.18.5.2 Sleep mode
7.18.5.3 Deep-sleep mode
7.18.5 Power control
The LPC1311/13/42/43 support a variety of power control features. There are three
special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC1311/01 and the LPC1313/01 for one of the following power modes:
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
Up to 40 pins total can serve as external wake-up pins to the start logic to wake up the
chip from Deep-sleep mode (see
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
•
•
•
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Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 6 June 2012
Section
7.19.1).
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
© NXP B.V. 2012. All rights reserved.
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