MK21DN512VMC5 Freescale Semiconductor, MK21DN512VMC5 Datasheet - Page 47

• Manufacturer Part Number: MK21DN512VMC5
• Description: ARM Microcontrollers - MCU ARM+512Kb+USB+DryIce
• Manufacturer: Freescale Semiconductor

Specifications of MK21DN512VMC5

• Core: ARM Cortex M4
• Processor Series: MK21DN512
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-121
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• Interface Type: Serial
• Length: 8 mm
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Freescale Semiconductor, Inc.
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
range the maximum frequency of operation is reduced.
Num
DS4
DS5
DS6
DS7
DS8
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Num
DS9
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 33. Master mode DSPI timing (full voltage range) (continued)
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Table 34. Slave mode DSPI timing (full voltage range)
Figure 18. DSPI classic SPI timing — master mode
K21 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
DS7
DS3
Description
First data
Description
DS8
First data
DS5
DS2
Data
Data
DS6
(t
BUS
Peripheral operating requirements and behaviors
DS1
Last data
20.5
Min.
-4.5
—
4
0
x 2) −
Last data
(t
SCK
8 x t
1.71
Min.
—
—
—
—
0
2
7
/2) - 4
DS4
BUS
Max.
10
—
—
—
—
(t
SCK/2)
Max.
6.25
3.6
20
19
19
—
—
—
—
Unit
ns
ns
ns
ns
ns
+ 4
MHz
Notes
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
3
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