MK21DN512VMC5 Freescale Semiconductor, MK21DN512VMC5 Datasheet - Page 41

• Manufacturer Part Number: MK21DN512VMC5
• Description: ARM Microcontrollers - MCU ARM+512Kb+USB+DryIce
• Manufacturer: Freescale Semiconductor

Specifications of MK21DN512VMC5

• Core: ARM Cortex M4
• Processor Series: MK21DN512
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-121
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• Interface Type: Serial
• Length: 8 mm
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

6.6.3.2 12-bit DAC operating behaviors
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to V
3. The DNL is measured for 0 + 100 mV to V
4. The DNL is measured for 0 + 100 mV to V
5. Calculated by a best fit curve from V
6. V
Freescale Semiconductor, Inc.
I
I
DDA_DACH
t
DDA_DACL
V
Symbol
CCDACLP
V
V
t
t
PSRR
DACHP
OFFSET
DACLP
dacouth
DNL
DNL
dacoutl
T
Rop
0x800, temperature range is across the full range of the device
T
BW
INL
SR
CT
E
P
P
CO
GE
DDA
G
= 3.0 V, reference select set for V
Supply current — low-power mode
Supply current — high-speed mode
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
Integral non-linearity error — high speed
mode
Differential non-linearity error — V
V
Differential non-linearity error — V
VREF_OUT
Offset error
Gain error
Power supply rejection ratio, V
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
Channel to channel cross talk
3dB bandwidth
Description
• High power (SP
• Low power (SP
• High power (SP
• Low power (SP
K21 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Table 28. 12-bit DAC operating behaviors
LP
LP
HP
HP
)
)
)
)
SS
DDA
+ 100 mV to V
DDA
DACR
DACR
DACR
DACR
DACR
≥ 2.4 V
(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
−100 mV
−100 mV
−100 mV with V
> 2
=
DACR
V
−100
0.05
Min.
550
DACR
1.2
60
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
− 100 mV
DDA
0.000421
> 2.4 V
±0.4
±0.1
0.12
Typ.
100
0.7
3.7
1.7
15
Peripheral operating requirements and behaviors
—
—
—
—
—
—
—
—
—
—
—
—
V
Max.
±0.8
±0.6
150
700
200
100
250
DACR
-80
30
±8
±1
±1
90
—
—
—
—
—
—
1
%FSR/C
%FSR
%FSR
μV/C
V/μs
LSB
LSB
LSB
Unit
kHz
mV
mV
μA
μA
dB
dB
μs
μs
μs
Ω
Notes
1
1
1
2
3
4
5
5
6
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