MK21DN512VMC5 Freescale Semiconductor, MK21DN512VMC5 Datasheet - Page 45

• Manufacturer Part Number: MK21DN512VMC5
• Description: ARM Microcontrollers - MCU ARM+512Kb+USB+DryIce
• Manufacturer: Freescale Semiconductor

Specifications of MK21DN512VMC5

• Core: ARM Cortex M4
• Processor Series: MK21DN512
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-121
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• Interface Type: Serial
• Length: 8 mm
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

6.8.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Freescale Semiconductor, Inc.
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Num
DS9
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
Table 31. Master mode DSPI timing (limited voltage range)
Table 32. Slave mode DSPI timing (limited voltage range)
Figure 16. DSPI classic SPI timing — master mode
K21 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
DS7
DS3
Description
First data
Description
DS8
First data
Table continues on the next page...
DS5
DS2
Data
Data
DS6
(t
(t
(t
SCK
BUS
BUS
2 x t
Peripheral operating requirements and behaviors
DS1
Last data
Min.
2.7
−2
15
—
—
/2) − 2
2
2
0
x 2) −
x 2) −
BUS
Last data
4 x t
Min.
2.7
(t
DS4
SCK
BUS
Max.
3.6
8.5
25
—
—
—
—
—
—
/2) + 2
Max.
12.5
3.6
—
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
MHz
Notes
Unit
ns
V
1
2
45