MK21DN512VMC5 Freescale Semiconductor, MK21DN512VMC5 Datasheet - Page 19

• Manufacturer Part Number: MK21DN512VMC5
• Description: ARM Microcontrollers - MCU ARM+512Kb+USB+DryIce
• Manufacturer: Freescale Semiconductor

Specifications of MK21DN512VMC5

• Core: ARM Cortex M4
• Processor Series: MK21DN512
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-121
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• Interface Type: Serial
• Length: 8 mm
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I
Freescale Semiconductor, Inc.
f
LPTMR_ERCLK
Symbol
other module.
f
f
Symbol
I2S_MCLK
I2S_BCLK
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
2
LPTMR external reference clock
I2S master clock
I2S bit clock
Description
C signals.
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
Table 9. Device clock specifications (continued)
K21 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Table 10. General switching specifications
DD
DD
DD
DD
DD
DD
DD
DD
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 2.7V
≤ 2.7V
≤ 2.7V
≤ 2.7V
Min.
100
100
1.5
50
—
—
—
—
—
—
—
—
Min.
2
—
—
—
Max.
Max.
12.5
13
36
24
12
36
24
—
—
—
—
—
7
6
16
4
Bus clock
Bus clock
cycles
cycles
Unit
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
1,
General
3
3
3
4
5
2
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