SSTUG32868ET/G,518 NXP Semiconductors, SSTUG32868ET/G,518 Datasheet - Page 9

• Manufacturer Part Number: SSTUG32868ET/G,518
• Description: IC BUFFER 1.8V 25BIT 176-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUG32868ET/G,518

• Logic Type: 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935284276518; SSTUG32868ET/G-T; SSTUG32868ET/G-T

NXP Semiconductors
Table 3.
SSTUG32868_1
Product data sheet
Symbol
QCKE0A F2
QCKE0B H8
QCKE1A E2
QCKE1B F8
QODT0A N2
QODT0B M7
QODT1A P2
QODT1B M8
Output error
QERR
Parity input
PAR_IN
Program inputs
CSGEN
Clock inputs
CK
CK
Miscellaneous inputs
RESET
VREF
V
DD
Pin
1 : 2 Register A (C = 0)
M3
L3
L2
L1
M1
M2
A5, AB5
B3, B4, B5, B6, D3, D4,
D5, D6, F3, F4, F5, F6, H3,
H4, H5, H6, K4, K5, K6,
M4, M5, M6, P4, P5, P6,
T3, T4, T5, T6, V3, V4, V5,
V6, Y3, Y4, Y5, Y6, AB4,
AB6
Pin description
…continued
1 : 2 Register B (C = 1)
U2
R8
V2
U8
K2
L7
J2
L8
M3
L3
L2
L1
M1
M2
A5, AB5
B3, B4, B5, B6, D3, D4,
D5, D6, F3, F4, F5, F6, H3,
H4, H5, H6, K4, K5, K6,
M4, M5, M6, P4, P5, P6,
T3, T4, T5, T6, V3, V4, V5,
V6, Y3, Y4, Y5, Y6, AB4,
AB6
Rev. 01 — 23 April 2007
1.8 V DDR2-1G configurable registered buffer with parity
Type
1.8 V
CMOS
outputs
1.8 V
CMOS
outputs
open-drain
output
SSTL_18
LVCMOS
input
differential
input
differential
input
LVCMOS
input
0.9 V
nominal
1.8 V
nominal
Description
Data outputs that will not be suspended
by the DCS0 and DCS1 control.
Data outputs that will not be suspended
by the DCS0 and DCS1 control.
Output error bit; generated on clock
cycle after the corresponding data
output.
Parity input. Arrives one clock cycle after
the corresponding data input.
Chip select gate enable. When HIGH,
the D1 to D28
only when at least one chip select input
is LOW during the rising edge of the
clock. When LOW, the D1 to D28
inputs will be latched and re-driven on
every rising edge of the clock.
Positive master clock input.
Negative master clock input.
Asynchronous reset input. Resets
registers and disables VREF data and
clock differential-input receivers.
Input reference voltage.
Power supply voltage.
SSTUG32868
[1]
inputs will be latched
© NXP B.V. 2007. All rights reserved.
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