SSTUG32868ET/G,518 NXP Semiconductors, SSTUG32868ET/G,518 Datasheet - Page 13

• Manufacturer Part Number: SSTUG32868ET/G,518
• Description: IC BUFFER 1.8V 25BIT 176-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUG32868ET/G,518

• Logic Type: 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935284276518; SSTUG32868ET/G-T; SSTUG32868ET/G-T

NXP Semiconductors
SSTUG32868_1
Product data sheet
Fig 6. Timing diagram during start-up (RESET switches from LOW to HIGH)
Dn, DODTn,
Qn, QODTn,
PAR_IN
DCKEn
(1) After RESET is switched from LOW to HIGH, all data and PAR_IN input signals must be set and held LOW for a minimum
(2) If the data is clocked on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be produced on
QERR
CSGEN
RESET
QCKEn
DCSn
time of t
the m + 2 clock pulse and it will be valid on the m + 3 clock pulse.
CK
CK
(1)
(1)
(2)
ACT(max)
7.3 Register timing
HIGH, LOW, or Don't care
to avoid false error.
t
ACT
m
HIGH or LOW
t
PDM
Rev. 01 — 23 April 2007
, t
CK to Q
PDMSS
t
su
1.8 V DDR2-1G configurable registered buffer with parity
data to QERR latency
m + 1
t
h
CK to QERR
t
su
t
PHL
m + 2
t
h
m + 3
SSTUG32868
CK to QERR
t
PHL
, t
© NXP B.V. 2007. All rights reserved.
PLH
m + 4
002aab899
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