SSTUG32868 NXP Semiconductors, SSTUG32868 Datasheet
SSTUG32868
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SSTUG32868 Summary of contents
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... DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 1. General description The SSTUG32868 is a 1.8 V 28-bit register specifically designed for use on two rank by four (2R is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs ...
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... SSTUG32868ET/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUG32868ET/G SSTUG32868ET/S SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity 15 mm, 0.65 mm ball pitch TFBGA package Package Name Description TFBGA176 plastic thin fine-pitch ball grid array package; ...
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... VREF DCKE0, DCKE1 DODT0, DODT1 DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 Fig 1. Logic diagram of SSTUG32868 (positive logic) SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity SSTUG32868 ...
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... Register B configuration ( D12, D17 to D20, D22, D24 to D28 Register B configuration (C = 1): Q1A to Q12A, Q17A to Q20A, Q22A, Q24A to Q28A Register B configuration (C = 1): Q1B to Q12B, Q17B to Q20B, Q22B, Q24B to Q28B Rev. 01 — 23 April 2007 SSTUG32868 PARITY GENERATOR ...
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... V DDR2-1G configurable registered buffer with parity SSTUG32868ET/G SSTUG32868ET/S ball A1 index area 002aac916 Transparent top view Rev. 01 — 23 April 2007 SSTUG32868 © NXP B.V. 2007. All rights reserved ...
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... Q21A GND D20 Q23A V DD D21 D22 GND D23 D24 V DD D25 D26 GND D27 D28 SELDR 176-ball grid; top view. Rev. 01 — 23 April 2007 SSTUG32868 GND VREF GND Q1A Q2A GND GND GND Q3A ...
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... D20 V DD (QCKE1A) D21 D22 GND (DCKE0) D23 D24 V DD (DCKE1) D25 D26 GND D27 D28 SELDR 176-ball grid; top view. Rev. 01 — 23 April 2007 SSTUG32868 GND VREF GND Q1A Q2A GND GND GND Q3A ...
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... Y8, AA8, AB8 N2 1.8 V CMOS M7 outputs P2 M8 Rev. 01 — 23 April 2007 SSTUG32868 Description The outputs of this register will not be suspended by the DCS0 and DCS1 control. The outputs of this register will not be suspended by the DCS0 and DCS1 control. Data inputs, clocked in on the crossing of the rising edge of CK and the falling edge of CK ...
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... H4, H5, H6, K4, K5, K6, M4, M5, M6, P4, P5, P6, T3, T4, T5, T6, V3, V4, V5, V6, Y3, Y4, Y5, Y6, AB4, AB6 Rev. 01 — 23 April 2007 SSTUG32868 Description Data outputs that will not be suspended by the DCS0 and DCS1 control. Data outputs that will not be suspended by the DCS0 and DCS1 control. ...
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... floating floating floating Rev. 01 — 23 April 2007 SSTUG32868 Type Description ground Ground. input LVCMOS Selects output drive strength: ‘HIGH’ for input with normal drive; ‘LOW’ for high drive. This weak pin will default HIGH if left open-circuit pull-up (built-in weak pull-up resistor) ...
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... LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus two clock cycles or until RESET is driven LOW. 7.2 Functional information The SSTUG32868 is a 28-bit configurable registered buffer designed for 1 1 All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS ...
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... NXP Semiconductors during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUG32868 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The SSTUG32868 includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device ...
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... V DDR2-1G configurable registered buffer with parity ACT PDM PDMSS QERR data to QERR latency HIGH or LOW Rev. 01 — 23 April 2007 SSTUG32868 PHL PHL PLH CK to QERR © NXP B.V. 2007. All rights reserved 002aab899 ...
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... PDM PDMSS data to QERR latency output signal is dependent on the prior unknown event Rev. 01 — 23 April 2007 SSTUG32868 PHL PLH CK to QERR HIGH or LOW © NXP B.V. 2007. All rights reserved. 4 002aab900 ...
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... Fig 8. Timing diagram during shutdown (RESET switches from HIGH to LOW) SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity t INACT t PHL RESET PLH RESET to QERR HIGH, LOW, or Don't care . Rev. 01 — 23 April 2007 SSTUG32868 HIGH or LOW 002aac511 © NXP B.V. 2007. All rights reserved ...
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... Human Body Model (HBM); 1 100 pF Machine Model (MM 200 pF Conditions [1] Dn and PAR_IN inputs [1] Dn and PAR_IN inputs [1] [1] Dn and PAR_IN inputs [2] RESET, CSGEN [2] RESET, CSGEN CK, CK CK, CK operating in free air SSTUG32868ET/G SSTUG32868ET/S Rev. 01 — 23 April 2007 SSTUG32868 Min Max 0.5 +2.5 [1][2] 0.5 +2.5 [1][ ...
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... Dn, CSGEN, PAR_IN inputs 250 mV 1 ref DD DCSn 0 600 mV; ICR 1 and CK 0 600 mV; ICR 1 RESET GND 1 instantaneous steady-state Rev. 01 — 23 April 2007 SSTUG32868 Min Typ Max ...
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... CK and from CK and CK to QERR from RESET to QERR from CK and CK to QERR from RESET to Qn from CK and Conditions from from (from (from Rev. 01 — 23 April 2007 SSTUG32868 Min Typ Max - - 450 [1][2] - ...
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... 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 23 April 2007 SSTUG32868 = 50 ; input slew rate = 1 V/ns 0 DUT delay = 350 OUT ( 0. ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 23 April 2007 SSTUG32868 V V ICR ref V IL 002aaa374 = V for LVCMOS inputs. ...
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... V DDR2-1G configurable registered buffer with parity 0 input slew rate = 1 V/ns 0 DUT OUT includes probe and jig capacitance. L output dv_f DUT OUT includes probe and jig capacitance. L dv_r output Rev. 01 — 23 April 2007 SSTUG32868 20 %, unless otherwise specified test point ( 002aaa377 ...
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... L LVCMOS RESET 0.5V t PLH output waveform 2 RESET input timing V ICR inputs t PHL output waveform 1 to clock inputs Rev. 01 — 23 April 2007 SSTUG32868 20 %, unless otherwise specified test point ( 002aaa500 0.15 V ...
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... Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity timing V ICR inputs t PLH output waveform 2 clock inputs Rev. 01 — 23 April 2007 SSTUG32868 V V i(p-p) ICR 002aab907 © NXP B.V. 2007. All rights reserved ...
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... 6.1 15.1 0.65 4.55 13.65 0.15 5.9 14.9 REFERENCES JEDEC JEITA MO-246 - - - Rev. 01 — 23 April 2007 SSTUG32868 detail 0.08 0.1 0.1 EUROPEAN PROJECTION SOT932-1 ISSUE DATE 06-01-11 06-01-16 © NXP B.V. 2007. All rights reserved ...
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... Solder bath specifications, including temperature and impurities SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity Rev. 01 — 23 April 2007 SSTUG32868 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 24. Rev. 01 — 23 April 2007 SSTUG32868 Figure 24) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2007. All rights reserved. ...
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... Dynamic Random Access Memory Low Voltage Complementary Metal Oxide Semiconductor Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic Data sheet status Product data sheet Rev. 01 — 23 April 2007 SSTUG32868 peak temperature 001aac844 Change notice Supersedes - - © NXP B.V. 2007. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 23 April 2007 SSTUG32868 © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SSTUG32868 All rights reserved. Date of release: 23 April 2007 Document identifier: SSTUG32868_1 ...