SSTUG32868ET/G,518 NXP Semiconductors, SSTUG32868ET/G,518 Datasheet
SSTUG32868ET/G,518
Specifications of SSTUG32868ET/G,518
SSTUG32868ET/G-T
SSTUG32868ET/G-T
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SSTUG32868ET/G,518 Summary of contents
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SSTUG32868 1.8 V 28-bit configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 1. General description The SSTUG32868 is a 1.8 V 28-bit register specifically designed for use ...
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... NXP Semiconductors I Two additional chip select inputs allow optional flexible enabling and disabling I Supports Stub Series Terminated Logic SSTL_18 data inputs I Differential clock (CK and CK) inputs I Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs I Single 1.8 V supply operation (1 2.0 V) ...
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... NXP Semiconductors 5. Functional diagram RESET VREF DCKE0, DCKE1 DODT0, DODT1 DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 Fig 1. Logic diagram of SSTUG32868 (positive logic) SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity ...
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... NXP Semiconductors RESET CK CK (1) Dn VREF PAR_IN DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 (2) Register A configuration (C = 0): Q1A to Q5A, Q7A, Q9A to Q12A, Q17A to Q28A (3) Register A configuration (C = 0): Q1B to Q5B, Q7B, Q9B to Q12B, Q17B to Q28B Fig 2 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for TFBGA176 SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity SSTUG32868ET/G SSTUG32868ET/S ball A1 index area 002aac916 Transparent top view Rev. 01 — 23 April 2007 SSTUG32868 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors Fig 4. Ball mapping ( Register SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity GND (DCKE1 (DCKE0) Q6A D9 GND (QCKE1A) Q8A D10 V DD (QCKE0A) D11 Q10A GND D12 Q12A V DD DCS1 QCS1A GND (D13) (Q13A) DCS0 QCS0A ...
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... NXP Semiconductors Fig 5. Ball mapping ( Register SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity GND Q6A GND D10 Q8A V DD D11 Q10A GND D12 Q12A V DD D13 Q13A GND (DODT1) (QODT1A) D14 Q14A DCS2 (DODT0) (QODT0A) CK CSGEN ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin Register Ungated inputs DCKE0 D1 DCKE1 C1 DODT0 N1 DODT1 P1 Chip Select gated inputs D1 to A2, A1, B2, B1, C2, C1, D28 D2, D1, E1, F1, G1, H1, N1, P1, R1, T1, U1, V1, W1, W2, Y1, Y2, AA1, AA2, AB1, AB2 Chip Select inputs ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Register QCKE0A F2 QCKE0B H8 QCKE1A E2 QCKE1B F8 QODT0A N2 QODT0B M7 QODT1A P2 QODT1B M8 Output error QERR M3 Parity input PAR_IN L3 Program inputs CSGEN L2 Clock inputs Miscellaneous inputs RESET M2 VREF A5, AB5 V B3, B4, B5, B6, D3, D4, DD D5, D6, F3, F4, F5, F6, H3, ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Register GND A4, A6, C3, C4, C5, C6, E3, E4, E5, E6, G3, G4, G5, G6, J3, J4, J5, J6, L4, L5, L6, N3, N4, N5, N6, R3, R4, R5, R6, U3, U4, U5, U6, W3, W4, W5, W6, AA3, AA4, AA5, AA6 SELDR AB3 [1] Data inputs = D1 to D5, D7 D12, D17 to D28 when ...
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... NXP Semiconductors Table 5. Parity and standby function table [1] RESET DCS0 DCS1 floating X or floating [1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function. [2] PAR_IN arrives one clock cycle after the data to which it applies. [3] This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW ...
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... NXP Semiconductors during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUG32868 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The SSTUG32868 includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device ...
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... NXP Semiconductors 7.3 Register timing RESET CSGEN DCSn CK CK Dn, DODTn, (1) DCKEn Qn, QODTn, QCKEn (1) PAR_IN (2) QERR HIGH, LOW, or Don't care (1) After RESET is switched from LOW to HIGH, all data and PAR_IN input signals must be set and held LOW for a minimum time avoid false error. ...
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... NXP Semiconductors RESET CSGEN DCSn CK CK Dn, DODTn, DCKEn Qn, QODTn, QCKEn PAR_IN (1) QERR unknown input event (1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked the QERR output signal will be generated on the clock pulse and it will be valid on the clock pulse error occurs and the QERR output is driven LOW, it stays LOW for a minimum of two clock cycles or until RESET is driven LOW ...
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... NXP Semiconductors RESET (1) CSGEN (1) DCSn (1) CK (1) CK Dn, DODTn, (1) DCKEn Qn, QODTn, QCKEn (1) PAR_IN QERR (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of t INACT(max) Fig 8. Timing diagram during shutdown (RESET switches from HIGH to LOW) ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O I continuous current through ...
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... NXP Semiconductors 10. Characteristics Table 8. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per MHz C input capacitance i Z output impedance o [1] Instantaneous is defined as within < following the output data transition edge. ...
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... NXP Semiconductors Table 9. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter f clock frequency clk t pulse duration W t differential inputs active ACT time t differential inputs inactive INACT time t set-up time su t hold time h [1] This parameter is not necessarily production tested. ...
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... NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) unless otherwise specified. The outputs are measured one at a time with one transition per measurement. ...
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... NXP Semiconductors Fig 12. Voltage waveforms; set-up and hold times Fig 13. Voltage waveforms; propagation delay times (clock to output) Fig 14. Voltage waveforms; propagation delay times (reset to output) SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity input V ref V = 600 mV. ...
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... NXP Semiconductors 11.2 Data output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 15. Load circuit, HIGH-to-LOW slew measurement Fig 16. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) C Fig 17. Load circuit, LOW-to-HIGH slew measurement Fig 18 ...
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... NXP Semiconductors 11.3 Error output load circuit and voltage measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 19. Load circuit, error output measurements Fig 20. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to Fig 21. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect ...
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... NXP Semiconductors Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity timing V ICR inputs t PLH output waveform 2 clock inputs Rev. 01 — 23 April 2007 SSTUG32868 V V i(p-p) ICR V OH ...
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... NXP Semiconductors 12. Package outline TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 0.7 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.35 0.80 0.45 mm 1.15 0.25 0.65 0.35 OUTLINE VERSION IEC SOT932 Fig 23. Package outline SOT932-1 (TFBGA176) ...
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... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 14. Acronym CMOS DDR2 DIMM DRAM LVCMOS PRR RDIMM SSTL 15. Revision history Table 15. ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 10 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 Functional information . . . . . . . . . . . . . . . . . . 11 7.3 Register timing . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Limiting values Recommended operating conditions ...