SSTUG32868ET/G,518 NXP Semiconductors, SSTUG32868ET/G,518 Datasheet - Page 18

• Manufacturer Part Number: SSTUG32868ET/G,518
• Description: IC BUFFER 1.8V 25BIT 176-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUG32868ET/G,518

• Logic Type: 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935284276518; SSTUG32868ET/G-T; SSTUG32868ET/G-T

NXP Semiconductors
Table 9.
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
[3]
Table 10.
Over recommended operating conditions, unless otherwise noted.
[1]
Table 11.
Over recommended operating conditions, unless otherwise noted.
SSTUG32868_1
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clk
W
ACT
INACT
su
h
clk(max)
PDM
PLH
PHL
PDMSS
This parameter is not necessarily production tested.
VREF must be held at a valid input voltage level, and data inputs must be held LOW for a minimum time of t
taken HIGH.
VREF, data and clock inputs must be held at valid voltage levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
Parameter
clock frequency
pulse duration
differential inputs active
time
differential inputs inactive
time
set-up time
hold time
Parameter
maximum clock frequency
peak propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
simultaneous switching
peak propagation delay
Timing requirements
Switching characteristics
Output edge rates
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
Conditions
CK, CK HIGH or LOW
DCSn before CK , CK
DODTn, DCKEn and Dn before CK , CK
PAR_IN before CK , CK
DCSn, DODTn, DCKEn and Dn after CK , CK
PAR_IN after CK , CK
Conditions
input
single bit switching;
from CK and CK to Qn
from CK and CK to QERR
from RESET to QERR
from CK and CK to QERR
from RESET to Qn
from CK and CK to Qn
Rev. 01 — 23 April 2007
Conditions
from 20 % to 80 %
from 80 % to 20 %
(from 20 % to 80 %) or
(from 80 % to 20 %)
1.8 V DDR2-1G configurable registered buffer with parity
[1]
[1]
Min
450
1.0
1.2
-
1
-
-
Min
1
1
-
[1][2]
[1][3]
INACT(max)
SSTUG32868
Min
-
1
-
-
0.6
0.5
0.5
0.4
0.4
Typ
-
-
-
-
-
-
-
Typ
-
-
-
after RESET is taken LOW.
ACT(max)
Typ
-
-
-
-
-
-
-
-
-
© NXP B.V. 2007. All rights reserved.
Max
-
1.4
3
3
2.4
3
1.5
Max
4
4
1
after RESET is
Max
450
-
10
15
-
-
-
-
-
Unit
MHz
ns
ns
ns
ns
ns
ns
Unit
V/ns
V/ns
V/ns
18 of 29
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns