HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 98

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
A Duty
B Duty
B Duty
A Duty
B Duty
B Duty
Period
CCRA
Period
Period
CCRA
Period
CCRP
CCRP
only be generated on the TPnB output pins. With the TnCCLR bit cleared to zero, the PWM period is
set using one of the eight values of the three CCRP bits, in multiples of 128. Now both CCRA and
CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their
relative TPnA and TPnB pins.
The TnPWM1 and TnPWM0 bits determine the PWM alignment type, which can be either edge or
centre type. In edge alignment, the leading edge of the PWM signals will all be generated concurrently
when the counter is reset to zero. With all power currents switching on at the same time, this may give
rise to problems in higher power applications. In centre alignment the centre of the PWM active
signals will occur sequentially, thus reducing the level of simultaneous power switching currents.
Interrupt flags, one for each of the CCRA, CCRB and CCRP, will be generated when a compare match
occurs from either the Comparator A, Comparator B or Comparator P. The TnAOC and TnBOC bits in
the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while
the two TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits pairs are used to enable the PWM output or to
force the TM output pin to a fixed high or low level. The TnAPOL and TnBPOL bit are used to reverse
the polarity of the PWM output waveform.
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
If f
The TP1A PWM output frequency = (f
The TP1B_n PWM output frequency = (f
50%.
If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value,
then the PWM output duty is 100%.
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
001b
001b
128
256
1
1
1
2
SYS
= 16MHz, TM clock source select f
010b
010b
256
512
2
2
2
4
011b
011b
384
768
3
3
3
6
SYS
100b
100b
1024
1022
98
512
511
511
511
/4) / 512 = f
(CCRA 2) 1
(CCRB 2) 1
(CCRB 2) 1
SYS
SYS
CCRA
CCRB
CCRB
/4) / 512 = f
/4, CCRP = 100b, CCRA = 128 and CCRB = 256,
101b
101b
1280
1024
640
512
512
512
SYS
/2048 = 7.8125kHz, duty = 128/512 = 25%.
SYS
/2048 = 7.8125kHz, duty = 256/512 =
110b
1021
1021
110b
1536
1021
2042
768
1022
1022
1792
1022
2044
111b
111b
896
February 9, 2011
000b
000b
1024
1023
1023
2046
1023
2046