HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 88

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
Bit 7
Bit 6~4
TM1DH
TM1C0
TM1C1
TM1C2
TM1DL
TM1AH
TM1BH
TM1AL
TM1BL
Name
Enhanced Type TM Register Description
Name
POR
R/W
Bit
TM1C0 Register
T1PAU
T1AM1
T1BM1
Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair
exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the
internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup
the different operating and control modes as well as the three CCRP bits.
Bit7
T1PAU
D7
D7
D7
T1PAU: TM1 Counter Pause Control
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
T1CK2~T1CK0: Select TM1 Counter clock
These three bits are used to select the clock source for the TM. Selecting the Reserved clock
input will effectively disable the internal counter. The external pin clock source can be chosen to
be active on the rising or falling edge. The clock source f
f
TBC
R/W
0: run
1: pause
000: f
001: f
010: f
011: f
100: f
101: Undefined
110: TCK1 rising edge clock
111: TCK1 falling edge clock
7
0
are other internal clocks, the details of which can be found in the oscillator section.
H
SYS
SYS
H
TBC
/64
/16
/4
T1AM0
T1BM0
T1CK2
Bit6
T1CK2
D6
D6
D6
R/W
6
0
10-bit Enhanced TM Register List
T1AIO1
T1BIO1
T1CK1
Bit5
T1CK1
D5
D5
D5
R/W
5
0
T1AIO0
T1BIO0
T1CK0
T1CK0
Bit4
D4
D4
D4
88
R/W
4
0
T1AOC
T1BOC
T1ON
Bit3
T1ON
D3
D3
D3
R/W
3
0
SYS
is the system clock, while f
T1APOL
T1BPOL
T1RP2
T1RP2
Bit2
D2
D2
D2
R/W
2
0
T1PWM1
T1CDN
T1RP1
T1RP1
Bit1
R/W
D1
D9
D1
D9
D1
D9
1
0
February 9, 2011
H
T1PWM0
T1CCLR
T1RP0
T1RP0
and
Bit0
R/W
D0
D8
D0
D8
D0
D8
0
0