HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 80

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Note:
Rev. 1.10
TM O/P Pin
Flag TnPF
Flag TnAF
CCRP Int.
CCRA Int.
Standard Type TM Operating Modes
TnPAU
TnPOL
0x3FF
CCRP
CCRA
TnON
1. With TnCCLR=0 a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to itsinitial state by a TnON bit rising edge
Counter Value
Compare Match Output Mode
Output pin set to
initial Level Low
if TnOC=0
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating
mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In
this mode once the counter is enabled and running it can be cleared by three methods. These are a
counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a
compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to 0.
CCRP=0
Counter overflow
Here TnIO [1:0] = 11
Toggle Output select
Output Toggle with
TnAF flag
Compare Match Output Mode -- TnCCLR = 0
CCRP > 0
Note TnIO [1:0] = 10
Active High Output select
CCRP > 0
Counter cleared by CCRP value
80
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Pause
Resume
TnCCLR = 0; TnM [1:0] = 00
Stop
Output controlled by
other pin-shared function
Counter
Restart
Output Pin
Reset to Initial value
Output Inverts
when TnPOL is high
February 9, 2011
Time