HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 40

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HT68F14

Manufacturer Part Number
HT68F14
Description
Enhanced I/O Flash Type MCU
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet

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Rev. 1.10
Bit 7
Bit 6 ~ 4
Bit 3 ~ 0
Watchdog Timer Control Register
Watchdog Timer Operation
Name
POR
R/W
Bit
WDTC Register
A single register, WDTC, controls the required timeout period as well as the enable/disable operation.
This register together with several configuration options control the overall operation of the Watchdog
Timer.
The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in
the application program and during normal operation the user has to strategically clear the Watchdog
Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the
clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown
location, or enters an endless loop, these clear instructions will not be executed in the correct manner,
in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer
options, such as enable/disable, clock source selection and clear instruction type are selected using
configuration options. In addition to a configuration option to enable/disable the Watchdog Timer,
there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional
enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the
configuration option being set to disable, the WDTEN3 ~ WDTEN0 bits must also be set to a specific
value of 1010B. Any other values for these bits will keep the Watchdog Timer enabled, irrespective of
the configuration enable/disable setting. After power on these bits will have the value of 1010. If the
Watchdog Timer is used, it is recommended that they are set to a value of 0101B for maximum noise
immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its
operation will result in no operation.
²x²: don¢t care.
FSYSON
FSYSON: f
WS2, WS1, WS0 : WDT time-out period selection
000: 256/f
001: 512/f
010: 1024/f
011: 2048/f
100: 4096/f
101: 8192/f
110: 16384/f
111: 32768/f
WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control
WDT Configuration Option
R/W
0: Disable
1: Enable
1010: Disable
Other: Enable
7
0
WDT Disable
WDT Disable
WDT Enable
S
S
SYS
S
S
S
S
S
S
WS2
R/W
Watchdog Timer Enable/Disable Control
Control in IDLE Mode
6
1
WS1
R/W
5
1
WDTEN3~WDTEN0 Bits
WS0
40
R/W
Except 1010
4
1
Enhanced I/O Flash Type MCU
1010
xxxx
HT68F13/HT68F14/HT68F15
WDTEN3
R/W
3
1
WDTEN2
R/W
Disable
Enable
Enable
2
0
WDT
WDTEN1
R/W
1
1
February 9, 2011
WDTEN0
R/W
0
0

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