HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 112

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt Operation
Name
POR
R/W
Bit
MFI1 Register - HT68F15
When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or
Comparator B match, etc., the relevant interrupt request flag will be set. Whether the request flag
actually generates a program jump to the relevant interrupt vector is determined by the condition of the
interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the
enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated
and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared
to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new
address which will be the value of the corresponding interrupt vector. The microcontroller will then
fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a
Here is located the code to control the appropriate interrupt. The interrupt service routine must be
terminated with a RETI , which retrieves the original Program Counter address from the stack and
allows the microcontroller to continue with normal execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own individual
vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is
serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be
cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other
interrupt requests occur during this interval, although the interrupt will not be immediately serviced,
the request flag will still be recorded.
JMP which will jump to another section of program which is known as the interrupt service routine.
unimplemented, read as 0
T1BF: TM1 Comparator B match Interrupt request flag
T1AF: TM1 Comparator A match interrupt request flag
T1PF: TM1 Comparator P match interrupt request flag
unimplemented, read as 0
T1BE: TM1 Comparator B match interrupt control
T1AE: TM1 Comparator A match interrupt control
T1PE: TM1 Comparator P match interrupt control
0: no request
1: interrupt request
0: no request
1: interrupt request
0: no request
1: interrupt request
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
7
T1BF
R/W
6
0
T1AF
R/W
5
0
112
T1PF
R/W
4
0
3
T1BE
R/W
2
0
T1AE
R/W
1
0
February 9, 2011
T1PE
R/W
0
0