HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 69

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.10
Bit 3
Bit 2
Bit 1
Bit 0
In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T0IO1 and T0IO0 bits only
after the TMn has been switched off. Unpredictable PWM outputs will occur if the T0IO1 and
T0IO0 bits are changed when the TM is running
T0OC: TP0_0, TP0_1 output control bit
Compare Match Output Mode
PWM Mode
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is
in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of
the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM
signal is active high or active low.
T0POL: TP0_0, TP0_1 output polarity control
This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
T0DPX: TM0 PWM period/duty Control
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
T0CCLR: Select TM0 Counter clear condition
This bit is used to select the method which clears the counter. Remember that the Compact TM
contains two comparators, Comparator A and Comparator P, either of which can be selected to
clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.
The T0CCLR bit is not used in the PWM Mode.
0: Initial low
1: Initial high
0: Active low
1: Active high
0: Non-invert
1: Invert
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
0: TM0 Comparatror P match
1: TM0 Comparatror A match
69
Enhanced I/O Flash Type MCU
HT68F13/HT68F14/HT68F15
February 9, 2011