HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 37

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
Entering the SLEEP0 Mode
Entering the SLEEP1 Mode
Entering the IDLE0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the HALT
instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT
and LVD both off. When this instruction is executed under the conditions described above, the
following will occur:
·
·
·
·
·
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit in SMOD register equal to ²0² and the WDT
or LVD on. When this instruction is executed under the conditions described above, the following will
occur:
·
·
·
·
·
There is only one way for the device to enter the IDLE0 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the
FSYSON bit in WDTC register equal to ²0². When this instruction is executed under the conditions
described above, the following will occur:
·
·
·
·
·
The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the ²HALT² instruction.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and stopped no matter if the WDT clock source originates from the f
clock or from the system clock.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
The system clock and Time Base clock will be stopped and the application program will stop at the
²HALT² instruction, but the WDT or LVD will remain with the clock source coming from the f
clock.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
f
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
The system clock will be stopped and the application program will stop at the ²HALT² instruction,
but the Time Base clock and f
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
f
clock.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
SUB
SUB
clock and the WDT is enabled. The WDT will stop if its clock source originates from the system
clock as the WDT is enabled.
SUB
clock will be on.
37
February 9, 2011
SUB
SUB