HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 31

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
NORMAL Mode
SLOW Mode
SLEEP0 Mode
SLEEP1 Mode
IDLE0 Mode
IDLE1 Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of its
functions operational and where the system clock is provided by one of the high speed oscillators. This
mode operates allowing the microcontroller to operate normally with a clock source will come from
one of the high speed oscillators, either the HXT, ERC or HIRC oscillators. The high speed oscillator
will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the
CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used,
running the microcontroller at a divided clock ratio reduces the operating current.
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from the low speed oscillator LIRC. Running the
microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode,
the f
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the f
stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to ²0².
If the LVDEN is set to ²1², it won¢t enter the SLEEP0 Mode.
The SLEEP Mode is entered when a HALT instruction is executed and the IDLEN bit in the SMOD
register is low. In the SLEEP1 mode the CPU will be stopped. However, the f
continue to operate if the LVDEN is set to ²1² or the Watchdog Timer function is enabled and if its
clock source is chosen via configuration option to come from the f
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be
stopped. In the IDLE0 Mode the Watchdog Timer clock, f
f
then f
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to
keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1
Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low
speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f
f
S
SYS
clock source. If the source is f
/4, then the f
H
S
is off.
will be on.
S
clock will be on, and if the source comes from f
SYS
/4, then the f
31
S
clock will be off, and if the source comes from f
S
, will either be on or off depending upon the
SUB
SUB
then f
.
S
, will be on. If the source is
S
will be on.
SUB
SUB
and f
and f
February 9, 2011
S
clocks will be
S
clocks will
SUB