HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 58

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

HM17CM256
- 58 -
(34-9) Increment control register set
notice
notice
notice
notice
notice
(reset :{WIN, AIM, AYI, AXI}=0
CS
0
possible by AIM, AYI, AXI register setting.
the address increment operation is possible without setting the read or write address by this register setting.
address should be used with auto increment mode set (AXI=”1”, AYI=”1”).
register when it is not auto increment mode.
end address.
by using this command. X, Y address is unknown after auto increment setting. When WIN register is set
to “1”, the RAM should be accessed after setting start point address and end point address.
end point of X address and Y address after WIN command setting ( WIN=”1”).
The relationship between AIM, AYI, AXI register and X, Y address increment mode is as follow.
Sets the display RAM address to increment mode when RAM data is accessed.
Per RAM write or read access, the increment or non-increment settings of X and Y address counter are
After setting the auto increment register, the X, Y address should be set lower bits first.
Please revise X, Y address register after increment register setting.
When WIN register is set to “1”, the CPU accesses specified area of display RAM. In this case X, Y
The window to be accessed is defined by setting the start X, Y address and end X, Y address.
When accessing display with window area mode, please set X, Y start address and then X, Y window
When accessing consecutive RAM area, it is possible to access next location without setting the address
And address setting should be done in sequence of start point of X address and Y address, and then
read
Y address is increased as followed loop regardless of REF register .
And X address is increased as followed loop according to REF register( SEG output direction setting
register ) value.
) Please refer to RAM address bitmap in (10) relation between display RAM and address
RS
1
AIM
AYI
This mode is valid when read or write is performed on consecutive RAM location.
This mode is valid when read out consecutive data and modifying the data and then write them in again or
Regardless of AIM setting, no auto increment for X and Y address
According to AIM setting, auto increment only for X address.
According to AIM setting, auto increment only for Y address
0
1
0
0
1
1
WIN=”0”: normal display RAM access
WIN=”1”: window area access at display RAM
RD
write per access.
1
AXI
WR
0
1
0
1
0
Both case of writing in and read out display RAM
Only when writing in display RAM( read modify)
RE
No increment
X address auto increment
Y address auto increment
X, Y address auto increment
0
H
2
, read address :A
RE
0
00
1
Increment timing selection
H
RE
0
Increment timing selection
0
H
) * : ”Don’t care”
Max
When accessing consecutive RAM areas by read or write,
D
1
H
7
D
0
6
D
1
5
D
0
4
WIN
D
3
Do not revise X, Y address
AIM
D
Remark
Remark
2
AYI
D
1
AXI
D
0