HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 17

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

(2) DDRAM and internal register access
address is shown directly after the end of the read command, so pay attention that assigned data is
available at 2nd timing step.
data bus D
falling edge of E (68 series).
until next cycle.
needs dummy read at the 2nd clock.
DDRAM / register select pin (RS), read / write control pin (RD) or WR pin.
There are rules at reading data out of display RAM, after address setting, the data of assigned
In other words, 1 cycle dummy read is needed after address setting and write cycle.
Write process starts after address setting and then the data on the 8bit data bus D
Internally, bus holder data is processed to data bus and data are written to bus holder from CPU
After address setting, data of assigned address are read at the 1st and 3rd clock, which means it
DDRAM and internal register are accessed by data bus D
When CS=“H”, it is in non-selective state and DDRAM and internal register access is impossible.
During access, Set CS=“L”.
Access selection to DDRAM or internal register is controlled by RS input.
caution) When 16 bit mode, do write in and read out by 16 bit not only RAM access but also command
BUS HOLDER
D
0
~D
TABLE
DATA WRITE IN OPERATION
DATA READ OUT OPERATION
setting.
7
D
(D
RS
H
WR
WR
WR
RD
L
0
~D
0
0
~D
~D
15
15
15
)
will be written in by CPU. The data is written at the rising edge of WR (80 series) or
Internal command register
address set
Display RAM data
Data contents
n
n
n
n
dummy
n+1
read
n+1
n address
data read
n+2
n
n+2
n+1 address
data read
0
n+3
n+1
~D
7
(D
n+3
0
~D
n+2 address
15
data read
), chip select pin (CS),
HM17CM256
n+4
n+2
n+4
0
~D
7
or 16bit
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