HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 16

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

HM17CM256
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(1-7) One systematization of CS when serial interface is selected
controls two chips to reduce control signal.
device and output at master device mode ) of slave chip.
point, only slave chip can be controlled.
selector state should be released (CS = “H”) after 9bit data transfer as shown in the following
figure.
CS
SDA
SCL
RS
In the multi-chip operation (master/slave) mode with serial I/F connection, one CS signal
Connect extended chip selection port (EXCS) of master chip to EXCS port ( input at slave
When EXCS is “L”, master chip cannot accept command except for EXCS control; at this
Slave device control is possible when CS = “L” period within EXCS = “L” state.
Serial clock (SCL) should go to “L” at the non-access period and after 9bit data transfer.
SDA and SCL signals are sensitive to external noise. To prevent miss operation chip
SCL
SDA
CS
RS
1
D
2
7
CS
SDA
SCL
RS
M/S
P/S
SMODE
SPOL
EXCS
CS
SDA
SCL
RS
M/S
P/S
SMODE
SPOL
EXCS
D
6
3
3line serial interface
(MASTER)
(SLAVE)
D
4
5
D
5
4
EXCS: expand CS signal ( input port )
P/S: parallel . serial selection port
M/S: master . slave selection port
SMODE: serial I/Fmode selection port
SPOL:command data bit polarity selection port
D
3
6
Access display RAM at SPOL=0:RS=0
Master device : output port
Slave device : input port
P/S=0: serial I/F
P/S=1: parallel I/F
M/S=0: slave operation
M/S=1: master operation
SMODE=0: 4 line serial I/F
SMODE=1: 3 line serial I/F
Access display RAM at SPOL=1:RS=1
At 3 line serial I/F mode
D
2
7
D
1
8
D
0
9
(input port)
(input port)
(input port)
(input port)