HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 18
HM17CM256
Manufacturer Part Number
HM17CM256
Description
128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HM17CM256.pdf
(111 pages)
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HM17CM256
(3) Read out of internal register
(4) 16 bit data access to DDRAM
(5) Display start line register
- 18 -
read (0~F
out 384bit data from DDRAM to LCD driver circuit.
display start line.
The data of Y address is displayed on the display start line depending on the value of the shift
command register and the display start line register.
Read out is possible not only from DDRAM, but also from the internal register. Addresses for
Read out is executed after writing read-out register address to internal register.
Internal register read out sequence
When register is read out, upper 4 bit data are “1111”.
Non-used bits of active registers are “0”.
When non-used registers are read out, upper 4 bits are “1111” and lower 4 bits are “0000”.
It is possible to write in DDRAM by 16-bits access with the data of 16 bits data bus D
16 bits data access mode is possible by setting the value of WLS register to “1”.
The data of this register are preset to the display line counter per FLM signal transition.
Line counter is counted up in synchronization with CL input and generates line address that read
Each command should be set to 8-bits(D
16-bit access is available at display RAM access.
When displaying the DDRAM data, it is the contents of Y address register that is corresponding to
TABEL
WLS
H
H
L
) are allocated in each register.
D
WR
RD
0
~D
7
register read
Address set
Acess mode
16 bit
8 bit
for
M
Internal register read address set
set RE of register to be read out
Internal register read
register read
RE register set:100
0
~D
Internal
7
m
) as well as to 16-bit access mode.
register read
Address set
for
N
register read
Internal
n
0
~D
15
.
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