HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 73

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

(34-27) Line inversion start address set
(34-28) Line inversion end address set
(34-29) Line inversion control
( reset :{LS
( reset :{LS
( reset :{LE
( reset :{LE
( reset :{PSC, BT, LREV}=0
CS
CS
address should be set first and then upper 3 bits are set later. The possible range is LS=00
CS
CS
CS
0
0
0
0
0
address(LEi) should be set as following condition.
When the start address of negative display is set on, it is set by this command.
The other values are forbidden. Please set the value under the condition, LS LE.
address should be set first and then upper 3 bits are set later.
condition, LS LE.
Setting the status of line inversion display tone.
LREV command : line inversion display ON/OFF setting.
The blink type display is controlled by BT command.
When line inversion display is ON(LREV=”1”), line inversion start address(LSi) and line inversion stop
And following condition is forbidden.
When the end address of negative display is set on, it is set by this command.
The possible range is LS=00
RS
RS
RS
RS
RS
1
1
1
1
1
3
6
3
6
~LS
~LS
~LE
~LE
LREV=”0”: normal display
LREV=”1”: line inversion display ON. The area specified by line inversion start/stop address is
RD
RD
RD
RD
RD
1
1
1
1
1
0
4
0
4
}=0
}=0
}=0
}=0
H
H
H
H
WR
WR
WR
WR
WR
, read address :4
, read address :5
, read address :6
, read address :7
0
0
0
0
0
blinked.
H
RE
RE
RE
RE
RE
, read address :8
1
1
1
1
1
2
2
2
2
2
H
RE
RE
RE
RE
RE
~4F
0
0
0
0
0
1
1
1
1
1
H
H
H
H
)
) * : “Don’t care”
)
) * : “Don’t care”
H
. The other values are forbidden. Please set the value under the
RE
RE
RE
RE
RE
1
1
1
1
1
0
0
0
0
0
LEi < LSi - (2)
LSi
H
) * : “Don’t care”
LEi - (1)
D
D
D
D
D
0
0
0
0
1
7
7
7
7
7
D
D
D
D
D
1
1
1
1
0
6
6
6
6
6
D
D
D
D
D
0
0
1
1
0
5
5
5
5
5
D
D
D
D
D
0
1
0
1
0
4
4
4
4
4
LS
LE
D
D
D
D
D
*
*
*
3
3
3
3
3
3
3
HM17CM256
LS
LS
LE
LE
D
D
D
D
D
*
2
2
2
2
2
2
6
2
6
The lower 4 bits of
The lower 4 bits of
H
LS
LS
~4F
LE
LE
BT
D
D
D
D
D
1
1
1
1
1
1
5
1
5
H
.
LREV
LS
LS
LE
LE
D
D
D
D
D
0
0
0
0
0
- 73 -
0
4
0
4