R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 97

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
2.17.1 Buffer status bit (BSTS)
2.17.2 Sending buffer monitor bit (INBUFM)
2.17.3 CSPLIT status clear of split transaction bit (CSCLR)
2.17.4 CSPLIT status of split transaction bit (CSSTS)
R e v 1 . 0 1
DIR Bit
This is the bit by which the controller displays whether access from the CPU to the FIFO buffer assigned to the pipe is
possible. The meaning of this bit differs according to the setup value of the DIR, BFRE and DCLRM bits.
Setup
When the pipe is set to transmit ("DIR=1"), the controller sets "1" to this bit when the software (or DMAC) writes the
data on at least one side in the FIFO buffer. The controller sets "0" in this bit when all the written data is transmitted
from the FIFO buffer. When the double buffer is used (if "DBLB=1" is written), "0" is displayed in this bit when the
controller has transmitted the data on both the sides and the software (or DMAC) has not completely written the data
on one side.
When the pipe is set to receive ("DIR=0"), this bit shows a value similar to the BSTS bit.
When the Host Controller function is selected, if the software writes "1" to this bit, the controller clears the CSSTS bit to
"0". In using the Split Transaction transfer, if the next transfer is restarted forcefully from the S-Split, use the software
to write "1" to this bit. Normally in a Split Transaction, since the controller automatically clears the CSSTS bit to "0"
when the C-Split is completed, software is not necessary for the clear process.
Not modify the CSSTS bit by using this bit except when the communication is stopped by "UACT=0" or when
confirmed that transfer is not complete due to detach detection.
"CSSTS=0" is not modified even if writing "1" to this bit when "CSSTS=0".
When the Peripheral Controller function is selected, write "0" to this bit.
When the Host Controller function is selected, the controller displays the C-Split status of the Split transaction in this
bit.
The controller sets "1" in this bit while starting the C-Split and sets "0" in this bit when the C-Split end is detected.
The setting of this bit shows the valid values only when the Host Controller function is selected.
Value
0
1
O c t 1 7 , 2 0 0 8
BFRE bit
Setup
Value
0
1
0
1
p a g e 9 7 o f 1 8 3
DCLRM Bit
Setup
Value
0
1
0
1
0
1
0
1
Table 2.17 BSTS Bit Operations
Sets "1" "when reading of the reception data of the FIFO buffer is
possible" and sets "0" when the data is read completely.
This combination cannot be written.
Sets "1" "when reading of the reception data of the FIFO buffer is
possible" and sets "0" when the software writes "BCLR=1" after reading
the data completely.
Sets "1" "when reading of the reception data of the FIFO buffer is
possible" and sets "0" when the data is read completely.
Sets "1" "when writing of the transmission data to the FIFO buffer is
possible" and sets "0" when the data is written completely.
This combination cannot be written.
This combination cannot be written.
This combination cannot be written.
Meaning of BSTS bit