R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 124

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.2.7
R e v 1 . 0 1
Control Transfer Stage Transition Interrupt
Figure 3.11 shows a diagram of the control transfer stage transition. The controller manages the control transfer
sequence and generates the control transfer stage transition interrupt. The control transfer stage transition interrupts
can be enabled or disabled individually in the INTENB0 register. The transitioned transfer stage can be confirmed in
the INTSTS0 register CTSQ bit.
The control transfer stage transition interrupt is only generated when the Peripheral Controller function is selected.
The control transfer sequence is as follows. When an error occurs, the DCPCTR register PID bit goes to “1X” (STALL).
Note that in the control write transfer data stage, if the number of receive data is more than the USB request wLength
value, the control transfer sequence error cannot be recognized. Also, in the control read transfer status stage, when a
packet other than a zero-length packet is received, an ACK response is returned and the transfer is successfully
completed.
When a CTRT interrupt (“SERR=1” setting) is generated due to a sequence error, “CTSQ=110” value is stored until
“CTRT=0” is written by software (interrupt status clear). Therefore, because “CTSQ=110” is being maintained, the
CTRT interrupt for the completion of the setup stage is not generated, even when a new USB request is received.
Events occurring after the setup stage are saved by the controller and the setup stage end interrupt is generated after
the interrupt status is cleared by software.
CTRT Interrupt
1Setup stage end
2Control read transfer status stage transition
3Control write transfer status stage transition
3Control transfer complete
5Control transfer sequence error
Receive setup
(1) Control Read Transfer
(2) Control Write Transfer
(3) No-Data Control Transfer
O c t 1 7 , 2 0 0 8
token
(a) OUT or PING token is received before any data transfer occurs corresponding to the data stage IN token
(b) IN token is received in the status stage
(c) The data packet received in the status stage is a “DATAPID=DATA0” packet
(a) IN token is received before any ACK response is sent corresponding to a data stage OUT token
(b) The first data packet received in the data stage is a “DATAPID=DATA0” packet
(c) OUT or PING token is received in the status stage
(a) OUT or PING token is received in the status stage
"CTSQ = 000"
Setup stage
Figure 3.11 Figure 3.11 Control Transfer Stage Transition
p a g e 1 2 4 o f 1 8 3
Send ACK
Send ACK
Send ACK
Receive setup
token
1
1
Control read data
Control write data
"CTSQ = 001"
"CTSQ = 011"
stage
stage
Control transfer
sequence error
"CTSQ = 110"
OUT token
In token
5
Detect error
2
3
1
Control read status
Control write status
No-data control
"CTSQ = 010"
"CTSQ = 100"
"CTSQ = 101"
status stage
stage
stage
When all stages within box
detect errors, the received
setup token is valid.
Receive ACK
Receive ACK
Send ACK
4
"CTSQ = 000"
4
Idle stage
Receive setup
token