R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 155

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.11 Pipe Schedule
3.11.1 Transaction Issuance Conditions
3.11.2 Transfer Schedule
3.11.3 USB Transmission Enable
R e v 1 . 0 1
*1)
*2)
*3)
*4)
When the Host Controller function is selected, the controller supplies the internal clock and transactions are issued in
the following conditions after “UACT=1” is set.
The following is a description of the scheduling method for transfers in a frames. The controller conducts transfers in
the following order after the SOF is sent. When using two ports and the combination of Port0 and Port1 transfer
speeds are the same as case (3) or (4) shown in Table 3.4, the scheduling is split between 2 lines. Each line is
scheduled in the order of steps (1) to (3). When the combination of Port0 and Port1 transfer speeds match cases (1) or
(2), the scheduling is performed in one line.
Setting the DVSTCTR register UACT bit to “1” starts the SOF or µSOF send and enables the transaction issuance.
Setting the UACT bit to “0” the controller stops the SOF or µSOF send and put the USB bus in the suspend status.
Slanted lines indicate this condition does not affect issuing of token.
”Valid” indicates transaction is issued only in transfer frame by interval counter in interrupt and isochronous
transfers. “Invalid” indicates transfer is issued regardless of interval counter.
Transaction is issued regardless of available receive area. The receive data will be corrupted if no receive area is
available.
Transaction is issued regardless of send data in buffer. A zero-length packet will be sent if the is no send data.
(1) Periodic transfer execution
(2) Control transfer setup transaction
(3) Bulk transfers, Data stage or status stage of the control transfer execution
O c t 1 7 , 2 0 0 8
The controller searches pipes in the following order until it finds a pipe enabled to issue an isochronous or
interrupt transfer transaction: Pipe 1
pipe, the transaction is issued.
The controller confirms the DCP. If it is setup transaction enabled, the setup packet is sent.
The controller searches the pipes in the order below. When it finds a pipe enabled for transaction in the bulk or
control transfer data stage or the control transfer status stage, the transaction is executed.
Search order: DCP
When the transaction is issued, the sequence goes on to the transaction in the next pipe whether the response
from the peripheral is ACK or NAK. Also, if there is time in the frame to execute another transfer, step (3) is
repeated.
Control transfer data
stage, status stage, and
bulk transfer
Isochronous transfer
Interrupt transfer
Transaction
Setup
p a g e 1 5 5 o f 1 8 3
Table 3.27 Transaction Issuance Conditions
Pipe 1
Pipe 2
OUT
OUT
OUT
DIR
IN
IN
IN
Pipe 2
Pipe 3
BUF
BUF
BUF
BUF
BUF
BUF
PID
Pipe 6
Pipe 4
Issuance Conditions
IITV *2)
invalid
invalid
valid
valid
valid
valid
Pipe 7
Pipe 5
Receive area
available
Send data in
buffer
Receive area
available
Send data in
buffer
Buffer status
Pipe 8
*3)
*4)
Pipe 9. When it finds an enabled
Set “1”
SUREQ