R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 11

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
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and it is a data transfer that does not use the CPU. This controller is equipped with 2-ch DMA interface and includes
the following functions:
the Host Controller function is selected, a pulse is output from the SOF_N pin at sending the SOF packet. When the
Peripheral Controller function is selected, a pulse is output from the SOF_N pin at receiving the SOF packet. When the
SOF packet is damaged, a pulse is output within the specified period according to the SOF interpolation timer.
isochronous transfer, are possible with this controller. The following are the pipe resources for each transfer type:
(1) Control transfer dedicated pipe - 1
(2) Interrupt transfer dedicated pipes - 4
(3) Bulk transfer dedicated pipes - 3
(4) Bulk transfer or isochronous transfer selection pipes - 2
(1) Transfer end notification function corresponding to the transfer end signal (DEND signal)
(2) FIFO buffer auto clear function while receiving a zero-length packet
(1) Cycle Steal Transfer
(2) Burst Transmission
USB data transfer
All types of data transfer of USB communication, such as control transfer, bulk transfer, interrupt transfer and
etc., according to the user system. This controller is equipped with an 8.5KB buffer memory. Allocate the buffer
memory according to the user system or execute the settings such as buffer operation mode, for the bulk transfer
dedicated pipe, and bulk transfer or isochronous transfer selection pipe. In buffer operations mode, high-performance
data transfer with low interrupt frequency is possible by using a double buffer configuration or continuous transfer
function of the data packet. A transfer completion function has been added, using the transaction counter function for
efficient data transfer rates of bulk and isochronous transfer pipes.
The user system control CPU and DMA controller access the buffer memory through three FIFO port registers.
Interface for access from DMAC
The DMA interface is the data transfer between the user system and this controller, in which the DxFIFO port is used,
This controller is equipped with an interface compatible with the two types of DMA transfers given below:
"CS_N, RD_N and WR_N" or DACK_N can be selected as the handshake signal (pin) of the DMA interface.
High-performance DMA transmission is possible in the DMA transmission by a split bus by modifying the data setup
timing using an OBUS bit operation of the DMAxCFG register.
SOF pulse output function
This controller is equipped with an SOF pulse output function that notifies the SOF packet send/receive timing. When
Write the USB transfer requirements for each pipe, such as transfer type, endpoint address, maximum packet size,
Assert and negate of the DREQ pin is repeatedly transmitted for one data transmission (1 byte/1 word).
This is a transmission in which the DREQ pin is asserted (not negated) until the transmission is completed, due to
the pipe buffer memory area allocated to the FIFO port or DEND signal.
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