R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 61

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
Remarks
* Bit number corresponds to the pipe number.
* If writing "BRDYM=0", to clear the status of each bit of this register, write "0" only to the bit that is to be cleared and "1" to other
bits.
* If writing "BRDYM=0", clear this interrupt before accessing the FIFO.
2.11.21 BRDY interrupt status bit of each pipe (PIPEBRDY)
2.11.21.1 Writing "BRDYM=0" and "BFRE=0"
R e v 1 . 0 1
♦ BRDY interrupt status register [BRDYSTS]
15-10 Unassigned. Fix to "0".
9-0
Bit
15
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PIPEBRDY
BRDY interrupt status of each pipe
When the BRDY interrupt is detected for the pipe with the controller, the controller sets "1" in the BRDYSTS register
PIPEBRDY bit. Here, by using the software when "1" is written to the bit corresponding to BRDYENB register, the
controller sets "1" to the INTSTS0 register BDY bit and asserts the interrupt from the INT_N pin.
For the BRDY interrupt, occurrence conditions and clearing method change according to the BRDYM and BFRE bits of
each pipe.
14
For these, the BRDY interrupt indicates the possibility of access to the FIFO port. In the following conditions, the
controller issues the internal BRDY interrupt request trigger and sets "1" in the PIPEBRDY bit corresponding to the
pipe for which a request trigger was issued.
(1) When the pipe is set to transmit
Request trigger is not issued for DCP (in other words, in data transmission of control transfer).
(2) When the pipe is set to receive
When the Peripheral Controller function is selected, this interrupt is not issued during communication with the control
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(a) When the software has modified the DIR bit from "0" to "1".
(b) When the controller ends the packet transmission of the pipe in the condition where write is not possible from
the CPU to the FIFO buffer that has been assigned to the pipe (when the BSTS bit read value is "0"). When set to
continuous transmission/reception, the request trigger is issued when transmission of one FIFO buffer is complete.
(c) When the FIFO buffer is set to double buffer, one side of the FIFO buffer is empty even if writing to other side is
completed. During writing to the FIFO buffer, the request trigger is not issued until write on other side is completed,
even if write on one side is completed.
(d) In an isochronous transfer type pipe, when the hardware causes a buffer flash.
(e) When the status of the FIFO bit has been modified from "write disabled" to "write enabled" by writing "1" to the
ACLRM bit.
(a) When the controller ends the packet transmission of the pipe in the condition where write is not possible from
the CPU to the FIFO buffer that has been assigned to the pipe (when the BSTS bit read value is "0"). A request
trigger is not issued for the transaction of data PID mismatch. When set to continuous transmission/reception mode,
the request trigger is issued when transmission of one FIFO buffer is complete. When a short packet is received,
the request trigger is issued even if space is available in the FIFO buffer. While using the transaction counter, a
request trigger is issued when a packet of setup value is received. Here, the request trigger is issued even if space
is available in the FIFO buffer.
(b) When the FIFO buffer is set to double buffer, if the FIFO buffer read is complete, one more FIFO buffer read
becomes possible. If one more buffer is received during read, the request trigger is not issued until the read of the
current buffer is completed.
O c t 1 7 , 2 0 0 8
13
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Name
12
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p a g e 6 1 o f 1 8 3
11
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10
?
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BRDY interrupt status of each pipe is set.
0: Interrupt not issued
1: Interrupt issued
9
0
-
8
0
-
Function
7
0
-
6
0
-
PIPEBRDY
5
0
-
4
0
-
Software Hardware Remarks
R/W(0)
3
0
-
2
0
-
<Address: 46H>
W
1
0
-
0
0
-