R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 67

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
♦ BEMP interrupt status register [BEMPSTS]
Remarks
* Bit number corresponds to the pipe number.
To clear the status shown by each bit of this register, write "0" only for the bit to be cleared and "1" for the other bits.
2.11.23 BEMP interrupt status bit of each pipe (PIPEBEMP)
R e v 1 . 0 1
15-10 Unassigned. Fix to "0".
9-0
Bit
15
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PIPENRDY
BEMP interrupt status of each pipe
For the pipe set as "PID=BUF" by the software, when the controller uses the software to detect the BEMP interrupt, it
sets "1" to the bit corresponding to the BEMPENB register. In this case, when using the software to write "1" to the bit
corresponding to the BEMPENB register, the controller sets "1" to the INTSTS0 register BEMP bit and asserts the
interrupt from the INT_N pin.
The controller issues an internal BEMP interrupt request in the following cases:
(1) In the transmission pipe, when the FIFO buffer of the corresponding pipe is empty on completion of transmission
(2) In the receiving pipe
The status can be cleared by writing "0" to this bit. No process is executed even if "1" is written to this bit.
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(including transmission of the zero-length packet). When it is a single buffer setting, for the pipe other than the DCP,
the internal BEMP interrupt request is issued simultaneously with the BRDY interrupt.
However, the internal BEMP interrupt request is not issued in the following cases:
(a) If writing to a double buffer, when the software (DMAC) starts the data write for the FIFO buffer on the CPU side
after completion of data transmission on one side.
(b) Buffer clear by writing "1" to the ACLRM bit or BCLR bit (empty).
(c) If writing to the Peripheral Controller function, IN transfer of control transfer status stage (zero-length packet
transmission)
When the data size greater than the setup value of the maximum packet size is received normally. In this case, the
controller issues the BEMP interrupt request, sets "1" in the bit corresponding to the PIPEBEMP bit, deletes the
reception data, and modifies the PID bit to "STALL"("11")". The controller does not give any response if writing to
the Host Controller function, and gives a STALL response if writing to the Peripheral Controller function.
However, the internal BEMP interrupt request is not issued in the following cases:
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(a) When a CRC error or bit stuffing error, etc., have been detected in the reception data
(b) While executing a Setup transaction
O c t 1 7 , 2 0 0 8
13
?
?
Name
12
?
?
p a g e 6 7 o f 1 8 3
11
?
?
10
BEMP interrupt status of each pipe is set.
0:interrupt not issued
1:interrupt issued
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9
0
-
8
0
-
Function
7
0
-
6
0
-
PIPEBEMP
5
0
-
4
0
-
Software Hardware Remarks
R/W(0)
3
0
-
2
0
-
W(1)
<Address: 4AH>
1
0
-
0
0
-