R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 168

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
4.10 Timing Diagrams
4.10.1 Index for register access timing diagram
4.10.2 Index for FIFO port access timing
R e v 1 . 0 1
Note: *1) Because the address signal is not used, the timing will be the same for the separate bus and multiplex bus.
of multiple signals, the rating from the falling edge will be valid starting from when the active delay signal changes. The
ratings from the rising edge will be valid starting from the change in signals that become inactive more quickly.
The reading and writing timing are carried out using a control signal. If the control signal is configured from a combination
Access
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
CPU
CPU
CPU
CPU
Bus Specifications
Separate bus
Separate bus
Multiplex bus
Multiplex bus
O c t 1 7 , 2 0 0 8
Specifications
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
SPLIT bus 2
CPU bus 2
CPU bus 1
CPU bus 1
CPU bus 3
CPU bus 3
CPU bus 1
CPU bus 1
CPU bus 1
CPU bus 1
CPU bus 3
CPU bus 3
CPU bus 1
CPU bus 1
CPU bus 0
CPU bus 0
CPU bus 0
CPU bus 0
CPU bus 2
CPU bus 2
CPU bus 2
Bus I/F
p a g e 1 6 8 o f 1 8 3
Access
Acknowledgement + RD/WR
Acknowledgement + RD/WR
Acknowledgement + RD/WR
Acknowledgement + RD/WR
CPU
CPU
CPU
CPU
I/F Specifications When
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Acknowledgement only
Separate bus
Separate bus
Separate bus
Separate bus
Separate bus
Separate bus
Multiplex bus
Multiplex bus
Multiplex bus
Multiplex bus
Multiplex bus
Multiplex bus
Operating
WRITE
WRITE
READ
READ
R/W
4.11.1.1
4.11.1.2
4.11.2.1
4.11.2.2
Index
DFORM
Bit Set
Value
010
010
000
000
100
100
100
100
011
011
000
000
010
010
000
000
100
100
100
100
100
100
011
011
000
000
-
-
-
-
Bit Set
OBUS
Value
1
1
0
0
1
1
1
1
0
0
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
R/W
CPU bus 0
CPU bus 0
CPU bus 0
CPU bus 0
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Cycle steal transfer
Note
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Burst transfer
Note
-
-
-
-
4.11.3.1
4.11.3.6
4.11.3.5
4.11.3.7
4.11.3.8
4.11.3.9
4.11.5.1
4.11.5.2
4.11.5.5
4.11.5.6
4.11.5.5
4.11.5.5
4.11.5.7
4.11.5.8
4.11.5.9
4.11.3.2
4.11.3.5
4.11.5.6
4.11.1.2
4.11.2.1
4.11.2.2
4.11.3.3
4.11.3.4
4.11.4.1
4.11.4.2
4.11.5.3
4.11.5.4
4.11.6.1
4.11.6.2
Index
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1