R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 134

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.4.1.1 Buffer Status
3.4.1.2 Buffer Clear
R e v 1 . 0 1
Bit Name
Function
Register
Method
Setup
0 (receive
direction)
0 (receive
direction)
1 (send
direction)
1 (send
direction)
0 (receive
direction)
1 (send
direction)
1 (send
direction)
Table 3.11 shows the buffer statuses for the controller. The buffer memory status can be confirmed with the BSTS and
INBUFM bits. The direction of buffer memory access can be specified in the PIPExCFG register DIR bit or the
CFIFOSEL register ISEL bit (in the DCP setting).
The INBUFM bit is only valid in the send direction of pipes 1 to 5.
When the send-side transfer pipe is set to double buffer, the BSTS bit is used to determine the status of the CPU-side
buffer and the INBUFM bit is used to determine the status of the SIE-side buffer. If the write event to the FIFO port
using the CPU (DMCA) is slow and the buffer empty space cannot be determined by the BEMP interrupt, send
completion can be confirmed with the INBUFM bit.
Table 3.13shows the buffer memory clear conditions for the controller. The following 4 bits can clear the buffer
memory.
ISEL or DIR
DIR
O c t 1 7 , 2 0 0 8
CFIFOCTR register
DxFIFOCTR register
Clears the CPU-side
buffer memory of the
pipe assigned to the
CFIFO port or DxFIFO
port
Clear the buffer
memory by setting
“BCLR=1”.
(Automatically returns
to “BCLR=0”)
Invalid
0
1
Table 3.12 Figure 3.12 Buffer Status Confirmation with INBUFM Bit
INBUFM
BCLR
0
1
0
1
BSTS
p a g e 1 3 4 o f 1 8 3
Table 3.11 Buffer Status Confirmation with BSTS Bit
No receive data or now receiving. FIFO port is read-disabled.
Receive data is in FIFO buffer or zero-length packet is received. FIFO port is
read-enabled.
However, when zero-length packet is received the FIFO port is read-disabled and
the buffer must be cleared.
Send is not completed. FIFO port is write-disabled.
Send is completed. FIFO port is write-enabled.
Invalid
Send data transfer is complete. No send data in FIFO buffer
Send data is written from FIFO port. Send data is in FIFO buffer.
CFIFOSIE register
Clears the SIE-side
buffer memory of the
pipe assigned to the
CFIFO port.
Clear the buffer
memory by setting
“SCLR=1”.
(Automatically returns
to “SCLR=0”)
Table 3.13 Buffer Clear Bits
SCLR
Buffer Memory Status
Buffer Memory Status
DxFIFOSEL register
automatically clears the
buffer memory after data
is read from the specified
pipe. Convenient function
when using DMAC to
read data.
Refer to 3.4.3.4
Set “DCLRM=1” to enable
mode.
Set “DCLRM=0” to
disable mode.
DCLRM
PIPExCTR register
Clears the SIE-side buffer
memory of the
corresponding pipe by
writing “1” and “0”
consecutively to the
ACLRM bit.
Set “ACLRM=1” to enable
mode.
Set “ACLRM=0” to
disable mode.
ACLRM