K9F1G08Q0M-PIB0 SAMSUNG [Samsung semiconductor], K9F1G08Q0M-PIB0 Datasheet - Page 8
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K9F1G08Q0M-PIB0
Manufacturer Part Number
K9F1G08Q0M-PIB0
Description
1Gb Gb 1.8V NAND Flash Errata
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K9F1G08Q0M-PIB0.pdf
(38 pages)
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Figure 2-1. K9F1G08X0M (X8) Array Organization
Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram
V
V
(=1,024 Blocks)
64K Pages
CC
SS
NOTE : Column Address : Starting Address of the Register.
2nd Cycle
CE
RE
WE
3rd Cycle
4th Cycle
1st Cycle
Command
A
A
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
12
0
- A
- A
11
27
I/O 0
A
A
A
A
12
20
0
8
CLE
& High Voltage
2K Bytes
Page Register
Control Logic
2K Bytes
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Generator
Register
ALE PRE
I/O 1
A
A
A
A
13
21
1
9
I/O 2
A
A
A
WP
A
10
14
22
2
64 Bytes
64 Bytes
I/O 3
A
A
A
A
11
15
23
3
7
I/O 4
A
A
A
*L
16
24
I/O 0 ~ I/O 7
4
Global Buffers
(1024 + 32)Byte x 65536
Data Register & S/A
I/O Buffers & Latches
I/O 5
1024M + 32M Bit
A
A
Cache Register
A
*L
17
25
NAND Flash
5
8 bit
Y-Gating
ARRAY
1 Block = 64 Pages
(128K + 4k) Byte
I/O 6
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
1 Device = (2K+64)B x 64Pages x 1024 Blocks
A
A
A
*L
18
26
6
= (128K + 4K) Bytes
= 1056 Mbits
I/O 7
A
A
A
*L
19
27
FLASH MEMORY
7
Output
Driver
Row Address
Row Address
Column Address
Column Address
SAMSUNG
V
V
CC
SS
I/0 7
I/0 0