K9F1G08Q0M-PIB0 SAMSUNG [Samsung semiconductor], K9F1G08Q0M-PIB0 Datasheet - Page 12
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K9F1G08Q0M-PIB0
Manufacturer Part Number
K9F1G08Q0M-PIB0
Description
1Gb Gb 1.8V NAND Flash Errata
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K9F1G08Q0M-PIB0.pdf
(38 pages)
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
Program / Erase Characteristics
NOTE : 1. Max. time of
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
AC TEST CONDITION
(K9F1GXXX0M-XCB0 :TA=0 to 70 C, K9F1GXXX0M-XIB0:TA=-40 to 85 C
CAPACITANCE
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
NOTE : 1. X can be V
VALID BLOCK
NOTE :
1. The
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction.
K9F1GXXQ0M : Vcc=1.70V~1.95V, K9F1GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
K9F1GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9F1GXXU0M:Output Load (Vcc:3.0V +/-10%)
K9F1GXXU0M:Output Load (Vcc:3.3V +/-10%)
Input/Output Capacitance
Input Capacitance
Program Time
Dummy Busy Time for Cache Program
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Valid Block Number
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks
CLE
H
H
X
X
X
X
X
L
L
L
L
K9F1GXXX0M
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
Parameter
Item
ALE
X
H
H
X
X
X
X
L
L
L
L
IL
(1)
t
or V
CBSY
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
Parameter
(
T
Parameter
IH.
A
=25 C, V
depends on timing between internal program completion and data in
CE
H
X
X
X
X
L
L
L
L
L
L
.
CC
Refer to the attached technical notes for appropriate management of invalid blocks.
=1.8V/3.3V, f=1.0MHz)
Symbol
Symbol
C
N
C
WE
H
I/O
X
X
X
X
X
VB
IN
Spare Array
Main Array
Test Condition
RE
H
H
H
H
H
H
X
X
X
X
V
V
1 TTL GATE and CL=30pF
1004
IN
IL
Min
Symbol
=0V
=0V
t
t
t
PROG
Nop
CBSY
BERS
11
0V/V
K9F1GXXQ0M
WP
H
H
H
H
H
X
X
X
X
L
0V to Vcc
CC
Vcc/2
(2)
5ns
-
0V/V
Min
PRE
-
-
-
-
Typ.
Min
X
X
X
X
X
X
X
X
X
X
-
-
CC
-
(2)
Read Mode
Write Mode
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
Data Input
Data Output
Typ
300
3
2
-
-
FLASH MEMORY
1 TTL GATE and CL=100pF
1 TTL GATE and CL=50pF
1024
Max
Max
10
10
Command Input
Address Input(4clock)
Command Input
Address Input(4clock)
K9F1GXXU0M
0.4V to 2.4V
Mode
Max
700
700
4
4
3
1.5V
SAMSUNG
5ns
Blocks
Unit
Unit
pF
pF
cycles
cycles
Unit
ms
s
s