K9F1G08Q0M-PIB0 SAMSUNG [Samsung semiconductor], K9F1G08Q0M-PIB0 Datasheet - Page 32

• Manufacturer Part Number: K9F1G08Q0M-PIB0
• Description: 1Gb Gb 1.8V NAND Flash Errata
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis-
ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while
data stored in data register are programmed into memory cell.
After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Pro-
gram command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY)
and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data
registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy sta-
tus bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is
inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming
of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer
of data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal pro-
gramming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence
must be progammed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/
O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail
status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and
later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/
O 1 may be read together when I/O 0 is checked.
Figure 10. Cache Program
Figure 9. Random Data Input In a Page
R/B
R/B
R/B
I/Ox
I/Ox
80h
Col Add1,2 & Row Add1,2
80h
Col Add1,2 & Row Add1,2
70h
80h
Address &
Data Input
Data
Data Input*
Address &
Status
output
Col Add1,2 & Row Add1,2
Data
Address & Data Input
15h
Data
80h
t
Col Add1,2 & Row Add1,2
CBSY
(available only within a block)
15h
t
CBSY
70h
Address &
Data Input
Data
80h
Col Add1,2 & Row Add1,2
Status
output
Data Input
Address &
85h
15h
Data
t
80h
CBSY
Col Add1,2 & Row Add1,2
Address & Data Input
15h
Address &
Data Input
t
Col Add1,2
CBSY
Data
70h
31
Data
Check I/O1 for pass/fail
80h
Col Add1,2 & Row Add1,2
15h
Status
output
Data Input
Address &
Data
t
CBSY
10h
70h
15h
t
Status
output
PROG
t
CBSY
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
output
Status
80h
FLASH MEMORY
Col Add1,2 & Row Add1,2
80h
Col Add1,2 & Row Add1,2
70h
Data Input
Address &
Data
Address &
Data Input
Data
SAMSUNG
I/O
Fail
10h
15h
0
"1"
t
t
CBSY
PROG
"0"
70h
Pass