AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 73
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AM49BDS640AHD8I
Manufacturer Part Number
AM49BDS640AHD8I
Description
Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49BDS640AHD8I.pdf
(84 pages)
- Current page: 73 of 84
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AC CHARACTERISTICS)
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing
4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at
December 5, 2003
Address (hex)
a bank in the process of performing an erase or program.
the boundary crossing.
RDY(1)
RDY(2)
AVD#
Data
CLK
(stays high)
3C
C60
D60
00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
3D
C61
A D V A N C E
Figure 43. Latency with Boundary Crossing
Address boundary occurs every 64 words, beginning at address
D61
3E
C62
t
RACC
D62
Am49BDS640AH
C63
latency
3F
t
RACC
I N F O R M A T I O N
latency
C63
3F
t
RACC
D63
C63
3F
t
RACC
C64
40
D64
C65
41
D65
C66
42
D66
C67
43
D67
71
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