AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 14

• Manufacturer Part Number: AM49BDS640AHD8I
• Description: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
• Manufacturer: SPANSION [SPANSION]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note: Default active edge of CLK is the rising edge.
VersatileIO™ (V
The VersatileIO
to set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
V
Requirements for Asynchronous Read
Operation (Non-Burst)
To read data from the memory array, the system must
first assert a valid address on A22–A0, while driving
AVD# and CE# to V
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is
divided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
12
Operation
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
Synchronous Write
Standby (CE#)
Hardware Reset
Burst Read Operations
Load Starting Burst Address
Advance Burst to next address with appropriate
Data presented on the Data Bus
Terminate current Burst read cycle
Terminate current Burst read cycle via RESET#
Terminate current Burst read cycle and start
new Burst read cycle
IO
pin.
TM
(V
IL
IO
IO
. WE# should remain at V
) Control
) control allows the host system
A D V A N C E
Table 1. Device Bus Operations
CE#
H
H
L
L
L
L
X
L
L
X
L
IH
Am49BDS640AH
. The
I N F O R M A T I O N
OE#
H
L
L
H
X
X
X
X
X
X
L
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device.
tions, the inputs and control levels they require, and the
resulting output. The following subsections describe
each of these operations in further detail.
Address access time (t
stable addresses to valid output data. The chip enable
access time (t
addresses and stable CE# to valid data at the outputs.
The output enable access time (t
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
in asynchronous mode upon device power-up, or after
a hardware reset. This ensures that no spurious alter-
ation of the memory content occurs during the power
transition.
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous sequential burst
operation and linear burst operation of a preset length.
WE#
H
H
X
X
H
H
H
H
H
L
L
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
Addr In
Addr In
Addr In
Addr In
Addr In
A22–0
C E
Data Out
DQ15–0
Table 1
HIGH Z
HIGH Z
HIGH Z
HIGH Z
) is the delay from the stable
Burst
I/O
I/O
I/O
I/O
I/O
X
ACC
) is equal to the delay from
lists the device bus opera-
RESET#
H
H
H
H
H
H
H
H
H
L
L
OE
December 5, 2003
) is the delay from
Note)
(See
CLK
X
X
X
X
X
X
AVD#
X
X
H
X
X
L
L