AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 3

• Manufacturer Part Number: AM49BDS640AHD8I
• Description: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
• Manufacturer: SPANSION [SPANSION]

Am49BDS640AH
Stacked Multichip Package (MCP), Flash Memory and pSRAM
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode 64 Megabit (4
M x 16-Bit) Flash Memory, and 16 Mbit (1 M x 16-Bit) pSRAM
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
PERFORMANCE CHARCTERISTICS
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMD re-
serves the right to change or discontinue work on this proposed product without notice.
Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
Manufactured on 0.13 µm process technology
VersatileIO™ (V
— Device generates data output voltages and tolerates data
— 1.8V compatible I/O signals
— Contact factory for availability of 1.5V compatible I/O signals
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
— Zero latency between read and write operations
— Four bank architecture: 8Mb/24Mb/24Mb/8Mb
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
SecSi
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Sector Architecture
— Sixteen 4 Kword sectors and one hundred twenty-six 32
— Banks A and D each contain eight 4 Kword sectors and
— Sixteen 4 Kword boot sectors: eight at the top of the address
Minimum 1 million erase cycle guarantee per sector
20-year data retention at 125°C
— Reliable operation for the life of the system
Read access times at 66/54 MHz (C
— Burst access times of 11/13.5 ns at industrial temperature
— Synchronous latency of 56/69 ns
— Asynchronous random access times of 50/55 ns
Power dissipation (typical values, C
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
input voltages as determined by the voltage on the V
executing erase/program functions in other bank
Kword sectors
fifteen 32 Kword sectors; Banks B and C each contain
forty-eight 32 Kword sectors
range and eight at the bottom of the address range
range
TM
(Secured Silicon) Sector region
ADVANCE INFORMATION
IO
) Feature
Refer to AMD’s Website (www.amd.com) for the latest information.
L
L
=30 pF)
= 30 pF)
IO
pin
HARDWARE FEATURES
SOFTWARE FEATURES
Handshaking feature
— Provides host system with minimum possible latency by
— Reduced Wait-state handshaking option further reduces
Hardware reset input (RESET#)
— Hardware method to reset the device for reading array data
WP# input
— Write protect (WP#) function allows protection of the four
Persistent Sector Protection
— A command sector protection method to lock combinations
— Sectors can be locked and unlocked in-system at V
Password Sector Protection
— A sophisticated sector protection method to lock
ACC input: Acceleration function reduces programming
time; all sectors locked when ACC = V
CMOS compatible inputs, CMOS compatible outputs
Low V
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
— Backwards compatible with Am29F and Am29LV families
Data# Polling and toggle bits
— Provides a software method of detecting program and erase
Erase Suspend/Resume
— Suspends an erase operation to read data from, or program
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
monitoring RDY
initial access cycles required for burst accesses beginning
on even addresses
highest and four lowest 4 kWord boot sectors, regardless of
sector protect status
of individual sectors and sector groups to prevent program or
erase operations within that sector
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
operation completion
data to, a sector that is not being erased, then resumes the
erase operation
program command sequences
CC
write inhibit
Publication# 31105
Issue Date: December 5, 2003
IL
Rev: A Amendment0
CC
level