AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 22

• Manufacturer Part Number: AM49BDS640AHD8I
• Description: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
• Manufacturer: SPANSION [SPANSION]

Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. While in asynchronous mode, the
device automatically enables this mode when
addresses remain stable for t
matic sleep mode is independent of the CE#, WE#, and
OE# control signals. Standard address access timings
provide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. While in synchronous mode, the
device automatically enables this mode when either the
first active CLK level is greater than t
runs slower than 5 MHz. Note that a new burst opera-
tion is required to provide new data.
I
represents the automatic sleep mode current specifica-
tion.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of
resetting the device to reading array data. When
RESET# is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the device requires a time of t
20
CC6
IL
in the
but not within V
“DC Characteristics” section on page 45
SS
± 0.2 V, the standby current will
ACC
CC4
A D V A N C E
SS
). If RESET# is held
+ 60 ns. The auto-
± 0.2 V, the device
ACC
READY
or the CLK
(during
RP
Am49BDS640AH
, the
I N F O R M A T I O N
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asser ted when a
program or erase operation is not executing, the reset
operation is completed within a time of t
during Embedded Algorithms). The system can read
data t
Refer to the
RESET# parameters and to
ings,” on page 59
Output Disable Mode
When the OE# input is at V
disabled. The outputs are placed in the high imped-
ance state.
Figure 1. Temporary Sector Unprotect Operation
Notes:
1. All protected sectors unprotected (If WP# = V
2. All previously protected sectors are protected once
outermost boot sectors will remain protected).
again.
RH
after RESET# returns to V
“AC Characteristics” section on page 59
for the timing diagram.
Unprotect Completed
Program Operations
Temporary Sector
Perform Erase or
RESET# = V
RESET# = V
(Note 1)
(Note 2)
START
IH
, output from the device is
Figure 30, “Reset Tim-
ID
IH
IH
December 5, 2003
.
READY
IL
,
(not
for