AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 66
AM49BDS640AHD8I
Manufacturer Part Number
AM49BDS640AHD8I
Description
Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49BDS640AHD8I.pdf
(84 pages)
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AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The
64
Configuration Register must be set to the Synchronous Read Mode.
Addresses
AVD#
CLK
CE#f
WE#
V
Data
OE#
CC
f
Figure 34. Synchronous Program Operation Timings: CLK Latched Addresses
t
AS
555h
t
VCS
t
CAS
t
CSW
t
AVCH
Program Command Sequence (last two cycles)
t
A D V A N C E
WP
t
AVDP
A0h
t
AH
t
WC
t
WPH
PA
Am49BDS640AH
I N F O R M A T I O N
t
t
DH
DS
PD
t
CH
VA
t
WHWH1
Progress
Read Status Data
In
December 5, 2003
VA
Complete
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