AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 25
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AM49BDS640AHD8I
Manufacturer Part Number
AM49BDS640AHD8I
Description
Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49BDS640AHD8I.pdf
(84 pages)
Write Protect (WP#)
The Write Protect feature provides a hardware method
of protecting the four outermost sectors. This function
is provided by the WP# pin and overrides the previ-
ously discussed Sector Protection/Unprotection
method.
If the system asserts V
disables program and erase functions in the eight “out-
ermost” 4 Kword boot sectors.
If the system asserts V
reverts to whether sectors 0
set to be protected or unprotected. That is, sector pro-
tection or unprotection for these sectors depends on
whether they were last protected or unprotected using
the method described in
section on page
Note that the WP# pin must not be left floating or un-
connected; inconsistent behavior of the device may re-
sult.
Low V
When V
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets to reading array data. Subsequent writes
are ignored until V
must provide the proper signals to the control inputs to
prevent unintentional writes when V
V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
December 5, 2003
LKO
IL
, CE# = V
Addresses
.
CC
1Ah
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
CC
Write Inhibit
is less than V
IH
or WE# = V
34.
CC
is greater than V
IH
IL
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
on the WP# pin, the device
on the WP# pin, the device
Data
“PPB Program Command”
LKO
IH
–
. To initiate a write cycle,
3 and 266
, the device does not
A D V A N C E
Table 6. CFI Query Identification String
CC
LKO
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
–
is greater than
269 were last
. The system
Am49BDS640AH
CC
I N F O R M A T I O N
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-indepen-
dent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h any time the device is ready to read array
data. The system can read CFI information at the
addresses given in
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the AMD
site at the following URL:
http://www.amd.com/flash/cfi.
Alternatively, contact an AMD representative for copies
Description
Tables
6-9. To terminate reading
IL
and OE# = V
Tables
6-9. The
IH
during
23