AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 51
![no-image](/images/no-image-200.jpg)
AM49BDS640AHD8I
Manufacturer Part Number
AM49BDS640AHD8I
Description
Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49BDS640AHD8I.pdf
(84 pages)
- Current page: 51 of 84
- Download datasheet (2Mb)
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
December 5, 2003
cycles to seven cycles.
cycles to seven cycles. Clock is set for active falling edge.
Addresses
Addresses
AVD#
AVD#
CE#f
Data
Data
CLK
OE#
RDY
OE#
RDY
CE#
CLK
Hi-Z
t
t
AVC
ACS
t
t
AVC
Hi-Z
ACS
Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock)
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)
t
CR
t
CR
t
ACH
Aa
1
t
t
CES
ACH
Aa
t
1
AVD
t
A D V A N C E
CES
2
t
AVD
t
OE
2
4 cycles for initial access shown.
3
t
t
ACC
OE
7 cycles for initial access shown.
t
t
ACC
IACC
Am49BDS640AH
t
IACC
3
4
I N F O R M A T I O N
t
RACC
5
4
Da
6
5
t
BDH
t
RACC
t
RDYS
Da + 1
7
t
Da
BACC
t
BDH
t
RDYS
Da + 1
t
t
CEZ
t
OEZ
Da + n
BACC
t
Da + n
t
CEZ
OEZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
49
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