AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 92
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AM79C940JC/W
Manufacturer Part Number
AM79C940JC/W
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C940JCW.pdf
(144 pages)
- Current page: 92 of 144
- Download datasheet (2Mb)
DC CHARACTERISTICS (Continued)
Notes:
1. V
2. I
3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.
4. I
5. Test not implemented to data sheet specification.
6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
7. During the activation of SLEEP:
8. Parameter not tested.
9. For industrial temperature version, Max value is –150 A.
10. For industrial temperature version, Max value is +150 A.
92
Parameter
I
I
–The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR
–The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:
–The following input pin has its internal pull-up and TTL level translator disabled: TC.
–The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,
–The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+
–The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.
–AWAKE and RWAKE are reset to zero. I
Symbol
V
IL1
IL1
IL2
OZ
V
V
and TDO.
value remains to be determined.
DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.
R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R.
and DO.
OH
V
RXDTH
V
TXOFF
V
LTHS–
R
TXH
TXL
TXI
and I
= ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.
= TC, TDI, TCK, TMS.
applies to all three-state output pins and bi-directional pins.
TX
does not apply to open-drain output pins.
IL2
applies to all input only pins except DI , CI , and XTAL1.
RXD Post-Squelch
Negative Threshold (Peak)
RXD Switching Threshold
TXD and TXD Output
HIGH Voltage
TXD and TXD Output
LOW Voltage
TXD and TXD Differential
Output Voltage Imbalance
TXD and TXD Idle Output
Voltage
TXD Differential Driver Output
Impedance
TXD Differential Driver Output
Impedance
Parameter Description
DDSLEEP,
LRT = LOW
(Note 4)
DV
DV
DV
(Note 8)
(Note 8)
with either AWAKE set or RWAKE set, will be much higher and its
Test Conditions
SS
DD
DD
= 0V
= +5V
= +5V
DV
DV
–156
DD
Min
–35
–40
SS
–0.6
DV
DV
SS
Max
–90
+40
35
40
40
80
DD
+ 0.6
Unit
mV
mV
mV
mV
V
V
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