AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 79

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Programmer’s Register Model (continued)
Addr Mnemonic
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PHYCC
RCVCC
CHIPID
CHIPID
RNTPC
LADRF
PADR
MPC
IAC
–
–
–
–
–
Physical Layer (PHY) Configuration Control
80
40
20
10
08
04
02
01
Chip Identification Register LSB–CHIPID [7:0]
Chip Identification Register MSB–CHIPID [15:8]
Internal Address Configuration
80
40
20
10
08
04
04
02
01
Reserved
Logical Address Filter–8 bytes–8 reads or writes–LS Byte first
Physical 6 bytes–6 reads or writes–LS Byte
first
Reserved
Reserved
Missed Packet Counter–Number of receive packets missed
Reserved
Runt Packet Count–Number of runt packets addressed to this node
Receive Collision Count–Number of receive collision frames on network
Reserved
–
–
–
–
–
PHYADDR Reset Physical Address pointer
LOGADDR Reset Logical Address pointer
RWAKE
AWAKE
LNKFL
DLNKTST
REVPOL
DAPC
LRT
ASEL
ADDRCHG Address Change–Write to PHYADDR or LOGADDR after ENRCV
–
Remote Wake–10BASE-T, AUI and EADI features active during
Auto Wake–10BASE-T receive and LNKST active during sleep
Reversed Polarity–Reports 10BASE-T receiver wiring error
Low Receive Threshold–Extended distance capability
Disable Auto Polarity Correction–Detection remains active
AUI
sleep
Link Fail–Reports 10BASE-T receive inactivity
Auto Select–Select 10BASE-T port when active, otherwise
Disable Link Test–Force 10BASE–T port into Link Pass
Contents
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W as 0
R/W
R/W
R/W
RO
RO
79