AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 63

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 3
Bit 2
Bit 1
RNTPCO
MPCO
RCVINT
RCVCC (REG ADDR 27) is free
running.
RCVCCO is READ/CLEAR only.
It is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by
asserting the RESET pin or
SWRST bit.
Runt Packet Count Overflow.
Indicates that the Runt Packet
Count register rolled over at a
value of 255 runt packets. Runt
packets are defined as received
frames which passed the inter-
nal address match criteria but
did not contain a minimum of
64-bytes of data after SFD. The
INTR pin will be activated if
the corresponding
RNTPCOM = 0. Note that the
RNTPC value returned in the
Receive Frame Status (RFS2)
will freeze at a value of 255,
whereas this register based
version of RNTPC (REG ADDR
26) is free running.
RNTPCO is READ/CLEAR only.
It is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by
asserting the RESET pin or
SWRST bit.
Missed Packet Count Overflow.
Indicates that the Missed Packet
Count register rolled over at a
value of 255 missed frames.
Missed frames are defined as
received frames which passed
the
criteria but were missed due to a
Receive FIFO overflow, the
receiver being disabled (ENRCV
= 0) or an excessive receive
frame count (RCVFC > 15). The
INTR pin will be activated if the
corresponding mask bit MPCOM
= 0.
MPCO is READ/CLEAR only. It
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by
asserting the RESET pin or
SWRST bit.
Receive Interrupt. Indicates that
the host read the last byte/word
of a packet from the Receive
FIFO. The Receive Frame Sta-
tus is available immediately on
the next host read operation.
The INTR pin will be activated if
internal
address
mask
match
Am79C940
bit
Bit 0
Interrupt Mask Register (IMR)
This register contains the mask bits for the interrupts.
Read/write operations are permitted. Writing a one into
a bit will mask the corresponding interrupt. Writing a
zero to any previously set bit will unmask the corre-
sponding interrupt. Bit assignments for the register are
as follows:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
RES
BABLM
XMTINT
JABM
BABLM
CERRM
RCVCCOM Receive Collision Count Over-
Name
CERRM
RCVCCOM
the corresponding mask bit
RCVINTM = 0.
RCVINT is READ/CLEAR only.
It is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by acti-
vation of the RESET pin or
SWRST bit.
Transmit Interrupt. Indicates that
the MACE device has completed
the transmission of a packet and
updated the Transmit Frame
Status. The INTR pin will be
activated if the corresponding
mask bit XMTINTM = 0.
XMTINT is READ/CLEAR only.
It is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by acti-
vation of the RESET pin or
SWRST bit.
Description
Jabber Error Mask. JABM is the
mask for JAB. The INTR pin will
not be asserted by the MACE
device regardless of the state of
the JAB bit, if JABM is set. It is
cleared by activation of the
RESET pin or SWRST bit.
Babble Error Mask. BABLM is
the mask for BABL. The INTR
pin will not be asserted by the
MACE device regardless of the
state of the BABL bit, if BABLM
is set. It is cleared by activation
of the RESET pin or SWRST bit.
Collision Error Mask. CERRM is
the mask for CERR. The INTR
pin will not be asserted by the
MACE device regardless of the
state of the CERR bit, if CERRM
is set. It is cleared by activation
of the RESET pin or SWRST bit.
flow Mask. RCVCCOM is the
mask
Collision Count Overflow). The
INTR pin will not be asserted by
RNTPCOM
for
MPCOM
RCVCCO(Receive
(REG ADDR 9)
RCVINTM
XMTINTM
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